System and method for fabricating openings in a...

Details System and method for fabricating openings in a... System and method for fabricating openings in a...

2005-05-17

2005-05-17

Vinh, Lan (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S004000, C438S637000, C438S706000, C156S345240

Reexamination Certificate

active

06893974

ABSTRACT:
A system and method is provided herein to fabricate openings in a semiconductor topography using feed forward control of etch process parameters. In one embodiment, a method includes measuring one or more dimensional features of a semiconductor topography to obtain pre-etch values. The method also includes determining a statistical result of the pre-etch values and adjusting one or more processing parameters if the statistical result is less than a target value. Subsequently, the method includes etching the semiconductor topography based upon the statistical result to form one or more openings in the semiconductor topography. As such, the system and method described herein fabricates openings using feed forward control of the etch process parameters to compensate for structural variations within semiconductor topographies that may exist between wafer-to-wafer and/or between lot-to-lot. In this manner, the system and method advantageously fabricates openings having profiles and dimensions, which exhibit little to no deviation from a design specification.

REFERENCES:
patent: 6069090 (2000-05-01), Eriguchi
patent: 6248602 (2001-06-01), Bode et al.
patent: 6372634 (2002-04-01), Qiao et al.
patent: 6376262 (2002-04-01), Kempa et al.
patent: 6410357 (2002-06-01), Chang et al.
patent: 6635185 (2003-10-01), Demmin et al.

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