Semiconductor wafer

Details Semiconductor wafer Semiconductor wafer

2005-03-08

2005-03-08

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S627000, C257S521000, C438S149000, C438S479000, C438S517000

Reexamination Certificate

active

06864534

ABSTRACT:
To provide a semiconductor wafer having crystal orientations of a wafer for the support substrate and a wafer for the device formation shifted from each other, wherein two kinds of wafers having different crystal orientations in which a notch or an orientation flat is to be provided do not need to be prepared. One of two semiconductor wafers having a notch or an orientation flat provided in the same crystal orientation <110> is set to be a wafer (1) for the support substrate and the other is set to be a wafer for the device formation. Both wafers are bonded with the notches or orientation flats shifted from each other (for example, a crystal orientation <100> of the wafer for the device formation and the crystal orientation <110> of the wafer (1) for the support substrate are set to the same direction). The wafer for the device formation is divided to obtain an SOI layer (3). A MOS transistor (TR1) or the like is formed on the SOI layer (3).

REFERENCES:
patent: 3920492 (1975-11-01), Sugita et al.
patent: 5060043 (1991-10-01), Yasue
patent: 6174222 (2001-01-01), Sato et al.
patent: 56060061 (1981-05-01), None
patent: 01241854 (1989-09-01), None
patent: 05090117 (1993-04-01), None
patent: 06005569 (1994-01-01), None
patent: 8-213578 (1996-08-01), None
patent: 9-223667 (1997-08-01), None
patent: 9-246505 (1997-09-01), None
M. Bruel, et al., ““Smart Cut”: A Promising New SOI Material Technology”, Proceedings 1995 IEEE International SOI Conference, Oct. 1995, pp. 178-179.
N. Sato et al., “High-Quality Epitaxial Layer Transfer (ELTRAN) by Bond and Etch-Back of Porous Si”, Proceedings 1995 IEEE International SOI Conferance, Oct. 1995, pp. 176-177.
K. Ohmi, et al., “Water Jet Splitting of Thin Porous Si for ELTRAN”, Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials, Tokyo, 1999, pp. 354-355.
H. Sayama, et al., “Effect of <100> Channel Direction for High Performance SCE Immune pMOSFET with Less Than 0.15 μm Gate Length”, 1999 IEEE, IEDM, pp. 657-660.
Effect of <100> Channel Direction for High Performance SCE Immune pMOSFET with Less Than 0.15 μm Gate Length, H. Sayama, et al.; International Electron Devices Meeting 1999; IEDM. Technical Digest, Washington, DC; Dec. 5-8, 1999; New York, NY; IEEE US; pp. 657-660.
Smart Cut: A Promising New SOI Material Technology; Bruel, M. et al.; 1995 IEEE International SOI Conference Proceedings; Tuscon, Oct. 3-5, 1995; Proceedings of the Annual SOS/SOI Technology Conference, (From 1991 Proceedings of the International SOI Conference.) Silicon-on-Insulator Technology and Devices, New York, Oct. 3, 1995; pp. 178-179.
High-Quality Epitaxial Layer Transfer (Eltran) by Bond and Etch-Back of Porous Si; Sato, et al.; 1995 IEEE International SOI Conference Proceedings. Tuscon, Oct. 3-5, 1995; Proceedings of the Annual SOS/SOI Technology Conference. (From 1991 Proceedings of the International SOI Conference.) Silicon-On-Insulator Technology and Devices, New York, Oct. 3, 1995, pp. 176-177.
U.S. patent application Ser. No. 09/930,202, Ipposhi et al., filed Aug. 16, 2001.
U.S. patent application Ser. No. 10/406,289, Iwamatsu, filed Apr. 4, 2003.
U.S. patent application Ser. No. 10/461,352, Iwamatsu et al., filed Jun. 16, 2003.

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