Method and apparatus for decoupling tag and data accesses in...

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique

Reexamination Certificate

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C711S118000, C711S122000

Reexamination Certificate

active

06944724

ABSTRACT:
One embodiment of the present invention provides a system that decouples a tag access from a corresponding data access within a cache memory. The system operates by receiving a memory request at the cache memory, wherein the memory request includes an address identifying a memory location. Next, the system performs the tag access by looking up at least one tag from a tag array within the cache memory and comparing the at least one tag with a tag portion of the address to determine if a cache line containing the address is located in the cache memory. If the cache line containing the address is located in the cache memory but a data array containing the cache line is busy, the system performs the corresponding data access at a later time when the data array becomes free. Furthermore, if the memory request is for a load operation, the corresponding data access takes place without waiting for preceding load operations to complete.

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patent: 5377345 (1994-12-01), Chang et al.
patent: 5745729 (1998-04-01), Greenley et al.
patent: 6732236 (2004-05-01), Favor
patent: 2002/0188821 (2002-12-01), Wiens et al.
Publication entitled “Complexity/Performance Tradeoffs with Non-Blocking Loads,” by Keith I. Farkas et al., 8345 Computer Architecture News, Apr. 1994, No. 2, New York, XP000450352, pp. 211-222.
Publication entitled “The Alpha 21264 Microprocessor” by R.E. Kessler., IEEE, Mar.-Apr. 1999, XP000832024, pp. 24-36.

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