Methods and arrangements for enhancing domino logic

Details Methods and arrangements for enhancing domino logic Methods and arrangements for enhancing domino logic

2005-04-05

2005-04-05

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S095000

Reexamination Certificate

active

06876232

ABSTRACT:
Methods and arrangements for enhancing domino logic are disclosed. Embodiments include a keeper circuit to pull up a domino node in response an output of an output circuit when the domino node is at a high voltage and to stop pulling up the domino node before the output changes to a first logical output. Further embodiments include an accelerator circuit to pull down the domino node when the keeper circuit stops pulling up the domino node. The domino node may couple with a pre-charge circuit and be pre-charged to a high voltage during a first portion of a clock cycle. The domino node may also couple with a logic input circuit to pull down the domino node during a second portion of the clock cycle, causing the output circuit to change the output from low to high in response to logic signals.

REFERENCES:
patent: 6404235 (2002-06-01), Nowka et al.
patent: 6707318 (2004-03-01), Kumar et al.
patent: 6791365 (2004-09-01), Bosshart
Anis, M.H. et. al, “Energy-Efficient noise-Tolerant Dynamic Styles for Scaled-Down CMOS and MTCMOS Technologies”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Apr. 2002, pp. 71-78, v. 10, n. 2, IEEE, United States (Publisher Item Id. S 1063-8210(02)00485-7).

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