Input buffer circuit

Details Input buffer circuit Input buffer circuit

2005-09-13

2005-09-13

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Tri-state

With field-effect transistor

C326S068000, C327S108000

Reexamination Certificate

active

06943585

ABSTRACT:
Disclosed is an input apparatus used in a SSTL interface, which comprises a differential buffer for comparing an external input signal with a reference potential inputted from an external, and a CMOS buffer for buffering the external input signal. In the input apparatus, the CMOS buffer operates when a command signal or an address signal is not inputted from an external, and when a predetermined operation such as a refresh operation is performed, thereby reducing the power consumption in a standby mode. Further, in order to prevent the input apparatus from abnormally operating when the reference potential is not maintained in the normal operation range, a reference potential level detecting circuit is further included in the input apparatus, so that the CMOS buffer operates when the reference potential deviates from a predetermined normal operation range. Furthermore, in order to enable an input buffer to operate as the CMOS when an input signal fully swings, a circuit for detecting a potential of an input signal inputted from an external is further included in the input apparatus.

REFERENCES:
patent: 5440248 (1995-08-01), Brown et al.
patent: 6480030 (2002-11-01), Taguchi
patent: 6670836 (2003-12-01), Zivanovic

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