Single poly embedded EPROM

Details Single poly embedded EPROM Single poly embedded EPROM

2005-04-26

2005-04-26

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185050, C365S185140, C365S185280, C365S185100, C365S185270

Reexamination Certificate

active

06885587

ABSTRACT:
A novel structure of nonvolatile memory is disclosed. The non-volatile memory includes two serially connected PMOS transistors. The characteristic of the devices is that bias is not necessary to apply to the floating gate during the programming mode. Thus, the control gate is omitted for the structure or layout, thereby saving the space for making the control gate. The carrier may be “automatically injected” into floating gate for programming the status of the devices.

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patent: 6653183 (2003-11-01), Hung et al.
Kuriyoshi Yoshikawa, Seiichi Mori, Norihisa Arai, An EPROM Cell Structure for EPCD's Compatible with Single Poly-ST Gate Process, IEEE Transactions on Electron Device, vol 37, No. 3, Mar. 1990, P675-679.
Katsuhiko Ohsaki, Noriaki Asumoto, Shunichi Takagaki, A Single Poly EEPROM Cell Structure for Use in Standard CMOS Processes, IEEE Journal of Solid State Circuits, vol. 29, No. 3, 1994, p. 311-316.

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