Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2005-09-27
2005-09-27
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S063000, C365S149000, C365S189090
Reexamination Certificate
active
06950367
ABSTRACT:
A semiconductor integrated circuit includes a first DRAM circuit having a first memory cell array having a plurality of memory cells each including a first MOS transistor, and a first potential generating circuit which generates at least one potential used to operate the plurality of memory cells in the first memory cell array, the first DRAM circuit being formed in a semiconductor chip, and a second DRAM circuit having a second memory cell array having a plurality of memory cells each including a second MOS transistor different in characteristic from the first MOS transistor, and a second potential generating circuit which generates at least one potential used to operate the plurality of memory cells in the second memory cell array, the second DRAM circuit being formed in the semiconductor chip.
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Nikkei Microdevices, Jun. 1995, pp. 66-73.
Dinh Son T.
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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