Method of forming a field effect transistor and methods of...

Details Method of forming a field effect transistor and methods of... Method of forming a field effect transistor and methods of...

2005-09-06

2005-09-06

Lee, Eddie (Department: 2811)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S642000, C438S674000, C438S685000, C438S761000, C438S653000, C438S652000

Reexamination Certificate

active

06939799

ABSTRACT:
A method of forming integrated circuitry includes forming a field effect transistor gate over a substrate. The gate comprises polysilicon conductively doped with a conductivity enhancing impurity of a first type and a conductive diffusion barrier layer to diffusion of first or second type conductivity enhancing impurity received thereover. An insulative layer is formed over the gate. An opening is formed into the insulative layer to a conductive portion of the gate. Semiconductive material conductively doped with a conductivity enhancing impurity of a second type is formed within the opening in electrical connection with the conductive portion, with the conductive diffusion barrier layer of the gate being received between the semiconductive material of the gate and the semiconductive material within the opening. Other aspects are disclosed and claimed.

REFERENCES:
patent: 4847111 (1989-07-01), Chow et al.
patent: 4884123 (1989-11-01), Dixit et al.
patent: 4997785 (1991-03-01), Pfiester
patent: 5027185 (1991-06-01), Liauh
patent: 5083190 (1992-01-01), Pfiester
patent: 5164333 (1992-11-01), Schwalke et al.
patent: 5244835 (1993-09-01), Hachiya
patent: 5282972 (1994-02-01), Hanna et al.
patent: 5292677 (1994-03-01), Dennison
patent: 5304504 (1994-04-01), Wei et al.
patent: 5312768 (1994-05-01), Gonzalez
patent: 5318924 (1994-06-01), Lin et al.
patent: 5371396 (1994-12-01), Vinal et al.
patent: 5418398 (1995-05-01), Sardella et al.
patent: 5504039 (1996-04-01), Grivna
patent: 5510646 (1996-04-01), Forouhi et al.
patent: 5576579 (1996-11-01), Agnello et al.
patent: 5589415 (1996-12-01), Blanchard
patent: 5600165 (1997-02-01), Tsukamoto et al.
patent: 5604140 (1997-02-01), Byun
patent: 5633200 (1997-05-01), Hu
patent: 5637525 (1997-06-01), Dennison
patent: 5637903 (1997-06-01), Liao et al.
patent: 5640037 (1997-06-01), Blanchard
patent: 5641708 (1997-06-01), Sardella et al.
patent: 5652464 (1997-07-01), Liao et al.
patent: 5668037 (1997-09-01), Prall et al.
patent: 5710454 (1998-01-01), Wu
patent: 5718800 (1998-02-01), Juengling
patent: 5723357 (1998-03-01), Huang
patent: 5753528 (1998-05-01), Forouhi et al.
patent: 5770496 (1998-06-01), Roberts
patent: 5776823 (1998-07-01), Agnello et al.
patent: 5783850 (1998-07-01), Liau et al.
patent: 5796166 (1998-08-01), Agnello et al.
patent: 5818092 (1998-10-01), Bai et al.
patent: 5821140 (1998-10-01), Jost et al.
patent: 5828130 (1998-10-01), Miller et al.
patent: 5856237 (1999-01-01), Ku
patent: 5883418 (1999-03-01), Kimura
patent: 5909637 (1999-06-01), Charneski et al.
patent: 5910021 (1999-06-01), Tabara
patent: 5923999 (1999-07-01), Balasubramanyam et al.
patent: 5933741 (1999-08-01), Tseng
patent: 5969983 (1999-10-01), Thakur et al.
patent: 6001726 (1999-12-01), Nagabushnam et al.
patent: 6075262 (2000-06-01), Moriuchi et al.
patent: 6107195 (2000-08-01), Gittleman et al.
patent: 6107656 (2000-08-01), Igarashi
patent: 6479362 (2002-11-01), Cunningham
patent: 0 722 190 (1995-12-01), None
patent: 0 588 176 (1996-01-01), None
patent: 63012132 (1988-01-01), None
patent: 63012152 (1988-01-01), None
patent: 64-042857 (1989-02-01), None
patent: 64-072543 (1989-03-01), None
patent: 03-192768 (1991-08-01), None
patent: 06-204171 (1994-07-01), None
patent: 8017758 (1996-01-01), None
patent: 8279553 (1996-10-01), None
patent: 10093077 (1998-04-01), None
patent: 10-135460 (1998-05-01), None
patent: 97-0018661 (1997-04-01), None
Semiconductor Instruments—Tech. Bull., Applied Materials Centura 5200 RTP (Dec., 2004) pp. 2-7).
Stanley Wolf, “Silicon Processing for the VLSI Era: vol. 2,” Lattice Press, Sunset Beach, CA. (1990) pp. 273-276.
J. D. Hayden, F. K. Baker, S. A. Ernst, R. E. Jones, J. Klein, M. Lien, T. F. McNelly, T. C. Mele, H. Mendez, B-Y Nguyen, L. C. Parrillo, W. Paulson, J. R. Pfiester, F. Pintchovski, Y-C See, R. Sivan, B.M. Somero, and E.O. Travis, “A High Performance Half Micrometer Generation CMOS Technology for Fast SRAM's,” IEEE Trans. on Electron Devices, vol. 38, No. 4, (1991) pp. 876-886.
W-H. Chang, B. Davari, MR. Wordeman, Y. Taur, C. Hsu, and M. D. Rodriguez, “ A High Performance 0.25-um CMOS Technology: Design and Characterization,” IEEE Trans. on Electron Devices, vol. 39, No. 4, (1992), pp. 959-966.
J. Nulman, B. Cohen, and K. Ngan, “Titanium Silicide and Titanium Nitride Layers Formed in an Integrated Multichamber System,” Proc. VMIC Conference (1991), pp. 312-315.
William C. O'Mara, Robert B. Herring, and Lee P. Hunt, “Handbook of Semiconductor Silicon Technology,” Noyes Publ., Norwich, New York (1990), p. 684.

Affiliated with

Also associated with

Rating

Method of forming a field effect transistor and methods of... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming a field effect transistor and methods of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a field effect transistor and methods of... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3395191