Semiconductor memory apparatus, semiconductor apparatus,...

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Reexamination Certificate

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C365S154000, C365S230030

Reexamination Certificate

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06839268

ABSTRACT:
A semiconductor memory apparatus is provided with a memory array, a first global bit line connected to a sense amplifier, a second global bit line connected to a write amplifier, and a selection circuit for connecting a plurality of bit lines selectively to the first global bit line and the second global bit line.

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Osada et al., “A 2ns Access, 285MHz, Two-Port Cache Macro Using Double Global Bit-Line Pairs” ISSCC Digest of Technical Papers, pp. 402-403.
Kushiyami et al., “A 295MHz CMOS 1M (x256) Embedded SRAM Using Bi-directional Read/Write Shared Sense Amps and Self-Timed Pulsed Word-Line Drivers” ISSCC Digest of Technical Papers, Feb. 1995, pp. 304-305.
IEEE Journal of Solid State Circuits, vol. 23, No. 5, Oct. 1988, pp. 1048-1053.

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