Methods of providing an interlevel dielectric layer...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S622000, C438S623000, C438S631000, C438S634000, C438S645000, C438S647000, C438S648000

Reexamination Certificate

active

06844255

ABSTRACT:
The invention comprises methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry. In one implementation, a method of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry includes forming a conductive metal interconnect layer over a substrate. An insulating dielectric mass is provided about the conductive metal interconnect layer. The insulating dielectric mass has a first dielectric constant. At least a majority of the insulating dielectric mass is etched away from the substrate. After the etching, an interlevel dielectric layer is deposited to replace at least some of the etched insulating dielectric material. The interlevel dielectric layer has a second dielectric constant which is less than the first dielectric constant.

REFERENCES:
patent: 3919060 (1975-11-01), Pogge et al.
patent: 3954523 (1976-05-01), Magdo et al.
patent: 3979230 (1976-09-01), Anthony et al.
patent: 3998662 (1976-12-01), Anthony et al.
patent: 4063901 (1977-12-01), Shiba
patent: 4180416 (1979-12-01), Brock
patent: 4561173 (1985-12-01), Te Velde
patent: 5023200 (1991-06-01), Blewer et al.
patent: 5103288 (1992-04-01), Sakamoto et al.
patent: 5141896 (1992-08-01), Katoh
patent: 5149615 (1992-09-01), Chakravorty et al.
patent: 5171713 (1992-12-01), Matthews
patent: 5192834 (1993-03-01), Yamanishi et al.
patent: 5266519 (1993-11-01), Iwamoto
patent: 5286668 (1994-02-01), Chou
patent: 5298311 (1994-03-01), Bentson et al.
patent: 5380679 (1995-01-01), Kano
patent: 5461003 (1995-10-01), Havemann et al.
patent: 5464786 (1995-11-01), Figura et al.
patent: 5470801 (1995-11-01), Kapoor et al.
patent: 5488015 (1996-01-01), Havermann et al.
patent: 5494858 (1996-02-01), Gnade et al.
patent: 5496773 (1996-03-01), Rhodes et al.
patent: 5525857 (1996-06-01), Gnade et al.
patent: 5527737 (1996-06-01), Jeng
patent: 5554567 (1996-09-01), Wang
patent: 5555966 (1996-09-01), Figura et al.
patent: 5583078 (1996-12-01), Osenbach
patent: 5599745 (1997-02-01), Reinberg
patent: 5629238 (1997-05-01), Choi et al.
patent: 5654224 (1997-08-01), Figura et al.
patent: 5670828 (1997-09-01), Cheung et al.
patent: 5691565 (1997-11-01), Manning
patent: 5691573 (1997-11-01), Avanzino et al.
patent: 5723368 (1998-03-01), Cho et al.
patent: 5736425 (1998-04-01), Smith et al.
patent: 5744399 (1998-04-01), Rostoker et al.
patent: 5773363 (1998-06-01), Derderian et al.
patent: 5804508 (1998-09-01), Gnade et al.
patent: 5807607 (1998-09-01), Smith et al.
patent: 5808854 (1998-09-01), Figura et al.
patent: 5861345 (1999-01-01), Chou et al.
patent: 5882978 (1999-03-01), Srinivasan et al.
patent: 5883014 (1999-03-01), Chen et al.
patent: 5950102 (1999-09-01), Lee
patent: 5967804 (1999-10-01), Yoshizawa et al.
patent: 5970360 (1999-10-01), Cheng et al.
patent: 5981085 (1999-11-01), Ninomiya et al.
patent: 6001747 (1999-12-01), Annapragada
patent: 6028015 (2000-02-01), Wang et al.
patent: 6156374 (2000-12-01), Forbes et al.
patent: 6245439 (2001-06-01), Yamada et al.
patent: 6251470 (2001-06-01), Forbes et al.
patent: 6313046 (2001-11-01), Juengling et al.
patent: 6333556 (2001-12-01), Juengling
patent: 6347446 (2002-02-01), Luthra et al.
patent: 6350679 (2002-02-01), McDaniel et al.
patent: 0 542 262 (1993-05-01), None
patent: 0 923 125 (1999-06-01), None
Yoon et al,Monolithic Integration of 3-D Electropated Microstructures with Unlimited Number of Levels . . .IEEE International Micro-Electro Mechanical Systems Conference (1999) pp. 624-629.
Wolf et al., “Silicon Processing for the VLSI Era”; 1 Process Technology 429-437 (1986).
Watanabe et al.,A Novel Stacked Capacitor With Porous-Si Electrodes for High Density DRAMs, Microelectronics Research Laboratories, NEC Corporation, Japan, #3A-1, pp. 17-18 (pre-1998).
Stanley Wolf, Ph.D., “Silicon Processing for the VLSI Era”, vol. 1, Process Technology, Copyright 1986, Lattice Press.
Singer, Peter, “The New Low-k Candidate: It's a Gas”, (Technology News/Wafer Processing)Semiconductor International, 1 Page, (Mar. 1989.
Product Brochure and Material Safety Data Sheet, “Interlayer Dielectric”,JSR Microelectronics, 12 Pages (1997).
Togo, M., Et Al., “A Gate-Side Air-Gap Structure (GAS) To Reduce the Parasitic Capacitance in MOSFETs”,I.E.E.E., pp. 38-39 (1996).
Anand, M.B., Et Al., “Nura: A Feasible, Gas-Dielectric Interconnect Process”,I.E.E. E., pp. 82-83 (1996).
Abstract: Anderson, R.C., et al., “Porous Polycrystalline Silicon: A New Material For MEMS”,Journal of Microelectromechanical Systems, vol. 3, No. 1, pp. 10-18 (Mar. 1994).
Homma, Tetsuya, “Low Dielectric Constant Materials And Methods For Interlayer Dieletric Films In Ultralarge-Scale Integrated Circuit Multilevel Interconnections”,Material Science&Engr., R23, pp. 243-285 (1998).
Abstract: Townsend, P.H., et al., “SiLK Polymer Coating With Low Dieletric Constant and High Thermal Stability for ULSI Interlayer Dielectric”,The Dow Chemical Company, Midland, MI, 9 Pages, (Undated).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Methods of providing an interlevel dielectric layer... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods of providing an interlevel dielectric layer..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of providing an interlevel dielectric layer... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3393308

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.