Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

2005-07-26

2005-07-26

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185110, C365S185180, C365S185240

Reexamination Certificate

active

06922357

ABSTRACT:
A non-volatile semiconductor memory device enabling reading at high speed has a memory cell array including a plurality of memory cells arranged in a column direction and a row direction, each of the memory cells having first and second non-volatile memory elements that are controlled by one word gate and first and second control gates. One of the first and second non-volatile memory elements stores data, but the other does not function as an element which stores data.

REFERENCES:
patent: 5408115 (1995-04-01), Chang
patent: 5422504 (1995-06-01), Chang et al.
patent: 5494838 (1996-02-01), Chang et al.
patent: 5969383 (1999-10-01), Chang et al.
patent: 6177318 (2001-01-01), Ogura et al.
patent: 6248633 (2001-06-01), Ogura et al.
patent: 6255166 (2001-07-01), Ogura et al.
patent: 6549463 (2003-04-01), Ogura et al.
patent: 6587380 (2003-07-01), Kanai et al.
patent: 6587381 (2003-07-01), Kanai et al.
patent: 6646916 (2003-11-01), Kamei
patent: 6650591 (2003-11-01), Owa
patent: 6654282 (2003-11-01), Kanai
patent: 6686632 (2004-02-01), Ogura et al.
patent: 6697280 (2004-02-01), Natori
patent: 6704224 (2004-03-01), Natori
patent: 6707695 (2004-03-01), Owa
patent: 6707716 (2004-03-01), Natori
patent: 6707720 (2004-03-01), Kamei et al.
patent: 6707742 (2004-03-01), Kamei et al.
patent: 6710399 (2004-03-01), Kamei
patent: 6717854 (2004-04-01), Natori
patent: 6738291 (2004-05-01), Kamei et al.
patent: 6744106 (2004-06-01), Kanai
patent: 6757197 (2004-06-01), Kamei
patent: 6760253 (2004-07-01), Kamei
patent: 6778446 (2004-08-01), Natori
patent: 6781187 (2004-08-01), Owa
patent: 6785182 (2004-08-01), Kamei et al.
patent: H07-161851 (1995-06-01), None
patent: 2978477 (1999-09-01), None
patent: 2001-156188 (2001-06-01), None
Yutaka Hayashi et al., “Twin MONOS Cell With Dual Control Gates”, 2000, IEEE VLSI Technology Digest.
Kuo-Tung Chang et al., “A New SONOS Memory Using Source-Side Injection for Programming”, IEEE Electron Device Letters, vol. 19, No. 7, Jul. 1998, pp. 253-255.
Wei-Ming Chen et al., “A Novel Flash Memory Device With S Plit Gate Source Side Injection and ONO Charge Storage Stack (SPIN)”, 1997, VLSI Technology Digest, pp. 63-64.
U.S. Appl. No. 10/115,956, filed Apr. 5, 2002, Publication No. 2003-0072191.
U.S. Appl. No. 10/157,897, filed May 31, 2002, Publication No. 2003-0072194.
U.S. Appl. No. 10/193,066, filed Jul. 12, 2002, Publication No. 2003-0025149.
U.S. Appl. No. 10/193,602, filed Jul. 12, 2002, Publication No. 2003-0027411.
U.S. Appl. No. 10/197,643, filed Jul. 18, 2002, Publication No. 2003-0025150.
U.S. Appl. No. 10/246,708, filed Sep. 19, 2002, Publication No. 2003-0095443.
U.S. Appl. No. 10/373,166, filed Feb. 26, 2003, Publication No. 2003-0174558.
U.S. Appl. No. 10/385,506, filed Mar. 12, 2003, Publication No. 2003-0198103.

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