Speculative cache memory control method and multi-processor...

Details Speculative cache memory control method and multi-processor... Speculative cache memory control method and multi-processor...

2005-09-27

2005-09-27

Anderson, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S121000, C711S124000, C711S146000, C712S216000

Reexamination Certificate

active

06950908

ABSTRACT:
The processors #0to #3execute a plurality of threads whose execution sequence is defined, in parallel. When the processor #1that executes a thread updates the self-cache memory #1,if the data of the same address exists in the cache memory #2of the processor #2that executes a child thread, it updates the cache memory #2simultaneously, but even if it exists in the cache memory #0of the processor #0that executes a parent thread, it doesn't rewrite the cache memory #0but only records that rewriting has been performed in the cache memory #1.When the processor #0completes a thread, a cache line with the effect that the data has been rewritten recorded from a child thread may be invalid and a cache line without such record is judged to be effective. Whether a cache line which may be invalid is really invalid or effective is examined during execution of the next thread.

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