SRAM cell and integrated memory circuit using the same

Details SRAM cell and integrated memory circuit using the same SRAM cell and integrated memory circuit using the same

2005-01-25

2005-01-25

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S205000

Reexamination Certificate

active

06847542

ABSTRACT:
An SRAM cell comprising a first inverter comprising a first load element and a first driver NMOSFET, a second inverter comprising a second load element and a second driver NMOSFET and having input and output terminals cross-coupled to output and input terminals of the first inverter, respectively, a first transfer gate NMOSFET having a current path inserted between the first inverter and a first bit line and a gate connected to a word line, and a second transfer gate NMOSFET having a current path inserted between the second inverter and a second bit line and a gate connected to the word line, wherein a current drivability of the first inverter and the first transfer gate NMOSFET for the first bit line is set to be larger than that of the second inverter and the second transfer gate NMOSFET for the second bit line.

REFERENCES:
patent: 5627789 (1997-05-01), Kalb, Jr.
patent: 5831896 (1998-11-01), Lattimore et al.
patent: 6130470 (2000-10-01), Selcuk
patent: 6519176 (2003-02-01), Hamzaoglu et al.
Kevin Zhang, et al., “The Scaling of Data Sensing Schemes for High Speed Cache Design in Sub-0.18μm Technologies”, 2000 Smyposium on VLSI Circuits Digest of Technical Papers, 2000, pp. 226-227.

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