Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2005-05-17
2005-05-17
Dildine, R. Stephen (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C708S492000, C714S757000
Reexamination Certificate
active
06895545
ABSTRACT:
A K-bit information signal represented by a polynomial U(x) having a degree K−1 is received. The information signal is transformed to form a transformed information signal using a first transform represented by a polynomial G1(x) having a degree P. The transformed information signal is represented by a polynomial T(x) having a degree K+P−1. T(x) equals U(x)G1(x). An initial cyclic code represented by a polynomial R1(x) is generated for the transformed information signal using a second transform represented by a polynomial G2(x), where G2(x) has high-order leading-zero terms. R1(x) equals the remainder obtained by dividing T(x) by G2(x). The initial cyclic code is transformed to form a final cyclic code represented by a polynomial R2(x) using the first transform. R2(x) equals R1(x)/G1(x).
REFERENCES:
patent: 3703705 (1972-11-01), Patel
patent: 5862159 (1999-01-01), Seshan
patent: 9807238 (1998-02-01), None
Parhi, K.K.; A systematic approach for design of digit-serial signal processing architectures; Circuits and Systems, IEEE Transactions on , vol.: 38 , Issue: 4 , Apr. 1991 pp.: 358-375.*
Karlsson, M.et al.; A method for increasing the throughput of fixed coefficient digit-serial/parallel multipliers Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on , vol.: 2 , May 23-26, 2004 pp.: II-425-428.*
European Search Report issued in EP application No. EP 03 00 7893, mailed Feb. 3, 2004, 4 pages.
Matsushima et al., “Parallel Encoder And Decoder Architecture For Cyclic Codes”,IEICE Transactions On Fundamentals of Electronics, Communications And Computer Sciences, Institute of Electronics, vol. 79, No. 9, Sep. 9, 1996, pp. 1313-1323.
Albertengo et al., “Parallel CRC Generation”,IEEE Micro, vol. 10, No. 5, Oct. 1, 1990, pp. 63-71.
Derby, Jeff H., “High-Speed CRC Computation Using State-Space Transformations,”Proceedings of the IEEE Global Telecommunications Conference(GLOBECOM)2001, vol. 1:166-170, IEEE (Nov. 2001).
Glaise et al., “Fast CRC Calculation,”Proceedings of the 1993 IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 602-605, IEEE (Oct. 1993).
Hobson et al., “A High-Performance CMOS 32-Bit Parallel CRC Engine,”IEEE Journal of Solid-State Circuits 34(2):233-235, IEEE (Feb. 1999).
Joshi, S.M., et al., “A New Parallel Algorithm for CRC Generation,”Proceedings of IEEE International Conference on Communications 3:1764-1768, IEEE (Jun. 2000).
Pei, T. and Zukowski, C., “High-Speed Parallel CRC Circuits in VLSI,”IEEE Transactions on Communications 40(4):653-657, IEEE (Apr. 1992).
Sobski, A. and Albicki, A., “Parallel Encoder, Decoder, Detector, Corrector for Cyclic Redundancy Checking,”Proceedings of IEEE International Symposium on Circuits and Systems(ISCAS)6:2945-2948, IEEE (1992).
Parhi, K. and Messerschmitt, D., “Pipeline Interleaving and Parallelism in Recursive Digital Filters—Part I: Pipelining Using Scattered Look-Ahead and Decompositions,”IEEE Transaction on Acoustic, Speech, and Signal Processing 37(7):1099-1117, IEEE (Jul. 1989).
Parhi, K. and Messerschmidtt, D., “Static Rate-Optimal Scheduling of Interative Data-Flow Programs via Optimum Unfolding,”IEEE Transactions on Computers 40(2):178-195, IEEE (Feb. 1991).
Parhi, K., “Pipelining in Algorithms with Quantizer Loops,”IEEE Transactions on Circuits and Systems 38(7):745-754, IEEE (Jul. 1991).
Broadcom Corporation
Dildine R. Stephen
Sterne Kessler Goldstein & Fox PLLC
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