Magnetic memory device

Details Magnetic memory device Magnetic memory device

2005-07-05

2005-07-05

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S055000

Reexamination Certificate

active

06914806

ABSTRACT:
There is provided a MRAM capable of reading at any timing information of memory cells at different addresses connected to the same bit line. Specifically, a memory cell of an address (AD00) has MOS transistors (Q1, Q2) connected in series and a magnetic tunnel resistive element (MR00), which are disposed between bit lines (BL0a, BL0b). The gate electrodes of the MOS transistors (Q1, Q2) are respectively connected to word lines (WL0a, WL0b). Memory lines (ML0, ML1) are connected in common to a reference voltage source (VR1) via N-channel MOS transistors (Q3, Q31), and are respectively connected to current sources with a switch (S1, S2). The bit lines (BL0a, BL0b, BL1a, BL1b) are respectively connected to inputs of buffers with a switch (B1to B4), and their outputs are supplied to the corresponding sense amplifier (SA1).

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patent: 6549455 (2003-04-01), Yamada
patent: 2001-267524 (2001-09-01), None

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