System for controlling data transfer protocol with a host...

Details System for controlling data transfer protocol with a host... System for controlling data transfer protocol with a host...

2005-03-22

2005-03-22

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output command process

C710S022000, C710S052000, C710S308000, C710S310000, C710S314000, C709S212000

Reexamination Certificate

active

06871237

ABSTRACT:
The present invention is a data transfer protocol control system with a host bus interface that includes a transmitting/receiving command DMA, a transmitting data DMA and a receiving data DMA for controlling data transfer protocol with a host bus interface considering characteristic, usage frequency, simultaneous processing functions of the command DMA and the data DMAs. A host interface bus is efficiently used and bus usage ratio is distributed properly to support transfer flow properly and improve the entire system performance. The data transfer protocol control system with a host bus interface includes a transmitting/receiving command DMA for instructing the command DMA request buffer to read and write command message data, a transmitting data DMA for instructing the transmitting data DMA request buffer to read the command message data, a receiving data DMA for instructing the receiving data DMA request buffer to write the command message data and a data transfer protocol control device for putting read information, write information and message data on a host bus, receiving message data and a transfer response signal and delivering the message data through the response buffer of the corresponding DMA.

REFERENCES:
patent: 5828901 (1998-10-01), O'Toole et al.
patent: 6163820 (2000-12-01), Garrett et al.
patent: 6199137 (2001-03-01), Aguilar et al.
patent: 6400730 (2002-06-01), Latif et al.
patent: 6459698 (2002-10-01), Acharya
patent: 6651119 (2003-11-01), Ghodrat et al.

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