SOI chip with mesa isolation and recess resistant regions

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation

Reexamination Certificate

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Reexamination Certificate

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06864149

ABSTRACT:
A semiconductor-on-insulator structure includes a substrate and a buried insulator layer overlying the substrate. A plurality of semiconductor islands overlie the buried insulator layer. The semiconductor islands are isolated from one another by trenches. A plurality of recess resistant regions overlie the buried insulator layer at a lower surface of the trenches.

REFERENCES:
patent: 4072974 (1978-02-01), Ipri
patent: 5013681 (1991-05-01), Godbey et al.
patent: 5024723 (1991-06-01), Goesele et al.
patent: 5213986 (1993-05-01), Pinker et al.
patent: 5374564 (1994-12-01), Bruel
patent: 5468657 (1995-11-01), Hsu
patent: 5633588 (1997-05-01), Hommei et al.
patent: 5659192 (1997-08-01), Sarma et al.
patent: 5663588 (1997-09-01), Suzuki et al.
patent: 5739574 (1998-04-01), Nakamura
patent: 5759898 (1998-06-01), Ek et al.
patent: 5769991 (1998-06-01), Miyazawa et al.
patent: 5863830 (1999-01-01), Bruel et al.
patent: 5882981 (1999-03-01), Rajgopal et al.
patent: 5904539 (1999-05-01), Hause et al.
patent: 6143070 (2000-11-01), Bliss et al.
patent: 6159824 (2000-12-01), Henley et al.
patent: 6291321 (2001-09-01), Fitzgerald
patent: 6335231 (2002-01-01), Yamazaki et al.
patent: 6355541 (2002-03-01), Holland et al.
patent: 6358806 (2002-03-01), Puchner
patent: 6368938 (2002-04-01), Usenko
patent: 6407406 (2002-06-01), Tezuka
patent: 6410371 (2002-06-01), Yu et al.
patent: 6410938 (2002-06-01), Xiang
patent: 6429061 (2002-08-01), Rim
patent: 6486008 (2002-11-01), Lee
patent: 6750097 (2004-06-01), Divakaruni et al.
patent: 20020140031 (2002-10-01), Rim
Current, M.I., et al., “Atomic-Layer Cleaving and Non-Contact Thinning and Thickening for Fabrication of Laminated Electronic and Photonic Materials,” 2001 Materials Research Society Spring Meeting (Apr. 16-20, 2001).
Current, M.I., et al., “Atomic-layer Cleaving with SixGeyStrain Layers for Fabrication of Si and Ge-rich SOI Device Layers,” 2001 IEEE SOI Conference (Oct. 1-4, 2001), pp.11-12.
Langdo, T.A., et al., “Preparation of Novel SiGe-Free Strained Si on Insulator Substrates,” 2002 IEEE International SOI Conference (Aug. 2002) pp. 211-212.
Mizuno, T., et al., “Novel SOI p-Channel MOSFETs With Higher Strain in Si Channel Using Double SiGe Heterostructures,” IEEE Transactions on Electron Devices, vol. 49, No. 1 (Jan. 2002) pp. 7-14.
Rim, K., et al., “Fabrication and Analysis of Deep Submicron Strained-Si N-MOSFETs,” IEEE Transactions on Electron Devices, vol. 47, No. 7 (Jul. 2000) pp. 1406-1415.

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