Self-aligned floating-gate structure for flash memory device

Details Self-aligned floating-gate structure for flash memory device Self-aligned floating-gate structure for flash memory device

2005-07-05

2005-07-05

Weiss, Howard (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

Reexamination Certificate

active

06914291

ABSTRACT:
The self-aligned floating-gate structure with a high coupling ratio being formed by one masking photoresist step is disclosed by the present invention, which comprises a first conductive layer over a tunneling-dielectric layer being formed over a semiconductor substrate in an active region and two extended second conductive layers being separately formed over etched-back field-oxide layers in nearby STI regions. Each of the extended second conductive layers is defined by a sidewall dielectric spacer being formed over each sidewall of the active region for forming a first-type self-aligned floating-gate structure and is formed by a sidewall conductive spacer being formed over each sidewall of the active region for forming a second-type self-aligned floating-gate structure, wherein thin sidewall conductive spacers are formed over sidewalls of the extended second conductive layers to alleviate the corner field-emission effects.

REFERENCES:
patent: 3758794 (1973-09-01), Kosonocky
patent: 5635415 (1997-06-01), Hong
patent: 6171909 (2001-01-01), Ding et al.
patent: 6576537 (2003-06-01), Tseng
patent: 6617222 (2003-09-01), Coursey
Peter Van Zant, Microchip Fabrication:A practical guide to semiconductor processing, 2000, McGraw-Hill, New York, 4th dition, pp. 387

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