Shared sense amplifier scheme semiconductor memory device...

Details Shared sense amplifier scheme semiconductor memory device... Shared sense amplifier scheme semiconductor memory device...

2005-04-26

2005-04-26

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S205000, C365S207000

Reexamination Certificate

active

06885598

ABSTRACT:
A semiconductor memory device includes first and second select transistors arranged on both sides of a shared-scheme sense amplifier and connected to a bit line, and first and second memory cell arrays connected to the bit line via the first and second select transistors, respectively, the first and second memory cell arrays each including a plurality of memory cells each having a cell transistor and a ferroelectric capacitor. The device further includes a setting circuit which controls the first and second select transistors, thereby setting the first and second memory cell arrays in an operative state at the same time, and a control circuit which performs a test at the same time for the first and second memory cell arrays, which are set in the operative state at the same time by the setting circuit.

REFERENCES:
patent: 5903492 (1999-05-01), Takashima
patent: 6483737 (2002-11-01), Takeuchi et al.
patent: 6498743 (2002-12-01), Maruyama
patent: 6657883 (2003-12-01), Takashima
patent: 6807084 (2004-10-01), Wohlfahrt et al.
patent: 10-255483 (1998-09-01), None
patent: 2001-67898 (2001-03-01), None

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