Split latency decoding

Details Split latency decoding Split latency decoding

2005-01-18

2005-01-18

Young, Brian (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Reexamination Certificate

active

06844831

ABSTRACT:
A decode unit is coupled to receive instruction bytes and to dispatch instructions to an execution subsystem. The decode unit comprises circuitry divided into a pipeline including a plurality of pipeline stages, wherein the circuitry is configured to concurrently initiate decode of a plurality of instructions and to dispatch at least an initial instruction of the plurality of instructions from a first pipeline stage of the plurality of pipeline stages. Furthermore, the circuitry is configured to dispatch at least one remaining instruction of the plurality of instructions from a second pipeline stage of the plurality of pipeline stages. The second pipeline stage is subsequent to the first pipeline stage in the pipeline.

REFERENCES:
patent: 5872946 (1999-02-01), Narayan et al.
patent: 6272616 (2001-08-01), Fernando et al.
patent: 6546478 (2003-04-01), Keller et al.

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