Structure of a lateral diffusion MOS transistor in...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S330000, C257S347000

Reexamination Certificate

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06921942

ABSTRACT:
There is provided a semiconductor device structured so as to be mounted jointly with other devices on one chip, and capable of controlling a large current in spite of a small device area while having small on-resistance, thereby enabling a high voltage resistance to be obtained. In the case of NLDMOS, the semiconductor device comprises an N well layer, formed on a p-type semiconductor substrate, a P well layer formed in the N well layer, a source electrode formed in a source trench cavity within the P well layer, a gate electrode formed in at least one of gate trench cavities within the P well layer, through the intermediary of an oxide film, and a drain electrode formed in a drain trench cavity within the N well layer, and further, N+ diffused layers are formed, around the source trench cavity, the drain trench cavity, respectively.

REFERENCES:
patent: 5640034 (1997-06-01), Malhi
patent: 6188104 (2001-02-01), Choi et al.
patent: 6265744 (2001-07-01), Okumura
patent: 2002/0109184 (2002-08-01), Hower et al.
patent: 06-097450 (1994-04-01), None
patent: 07/074352 (1995-03-01), None
patent: 09-139438 (1997-05-01), None
patent: 10-294463 (1998-11-01), None
patent: 2002-237591 (2002-08-01), None

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