SRAM memory cell, memory cell arrangement and method for...

Details SRAM memory cell, memory cell arrangement and method for... SRAM memory cell, memory cell arrangement and method for...

2005-04-19

2005-04-19

Wille, Douglas (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S212000

Reexamination Certificate

active

06882007

ABSTRACT:
The invention relates to an SRAM memory cell, a memory cell arrangement and a method for fabricating a memory cell arrangement. The SRAM memory cell has six vertical transistors, of which four are connected up as flip-flip transistors and two are connected up as switching transistors, four of the vertical transistors being arranged at corners of the rectangular base area.

REFERENCES:
patent: 5364810 (1994-11-01), Kosa et al.
patent: 20020006698 (2002-01-01), Noble
patent: 20020027802 (2002-03-01), Noble
Subbanna, S., et al., A High-Density 6.9 sq. μm Embedded SRAM Cell in a High-Performance 0.25 μm- Generation CMOS Logic Technology, IEDM 96, pp. 275-278 (1996).
Lage, C., et al., Advanced SRAM Technology—The Race Between 4T and 6T Cells, IEDM 96, pp. 271-274 (1996).

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