Shared peripheral architecture

Details Shared peripheral architecture Shared peripheral architecture

2005-07-05

2005-07-05

Rinehart, Mark H. (Department: 2112)

Electrical computers and digital data processing systems: input/

Access arbitrating

Access prioritizing

C710S051000

Reexamination Certificate

active

06915367

ABSTRACT:
A disk drive controller including a plurality of processors and a plurality of shared peripheral units. A shared bus couples the peripheral units and the processors. A bi-directional multiplexor selectably couples each of the plurality of processors to the shared bus in response to an owner signal. A set of peripheral-share registers where a first member of the set includes an entry associated with each of the plurality of peripheral units and holds a state value indicating which of the plurality of processors currently owns the associated peripheral unit.

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