Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2005-07-26
2005-07-26
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
06922799
ABSTRACT:
The object of the present invention is to provide a semiconductor memory device wherein analog data signal potential read out from a memory cell to bit-line (bit-line read-out potential) can be measured precisely. In this invention, a sense part circuit block140differentially amplifies data signal occurring on one of a pair of bit-lines (for example, bit-line BLNk, BLTk) in a memory cell array110, and reference signal occurring on another of the pair, and data is read out. Bit-lines BLN1, BLT1, -, BLNn, BLTn are connected to a reference potential setup circuit block150. Reference potential setup circuit150sets up potential assigned from outside of the device as potential of reference signal on bit-line. Bit-line read-out potential is indirectly obtained from the differential amplification result by controlling the reference potential with the reference potential setup circuit block150.
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Abraham Esaw
De'cady Albert
NEC Corporation
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