Transistor with improved source/drain extension dopant...

Details Transistor with improved source/drain extension dopant... Transistor with improved source/drain extension dopant...

2002-11-05

2004-06-01

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S663000

Reexamination Certificate

active

06743705

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
The present embodiments relate to electronic circuits and are more particularly directed to electronic circuit transistors having source/drain extensions.
Semiconductor devices are prevalent in all aspects of electronic circuits, and the design of such circuits often involves a choice from various circuit elements such as one or more different transistor devices. For example, in various applications including many high performance applications, transistors are formed with regions that are sometimes referred to either as drain extensions or source/drain extensions, where either name is used because the region extends the source/drain of the transistor to the area under the transistor gate. Several years ago such extensions were formed in some applications using “lightly-doped drain” extensions, typically identified with the abbreviation LDD. More recently, a comparable structure also extending under the gate channel has been formed, but the amount of dopant concentration in what formerly were the LDD extensions has increased. As a result, these regions are more recently referred to as HDD extensions due to the higher dopant concentration. For the sake of a consistent explanation in this document, all such regions will be referred to generally as source/drain extensions.
By way of further background, the following Figures and discussion illustrate one prior art approach for forming a MOS transistor that includes source/drain extensions, and by way of example a PMOS transistor is shown with it understood that various comparable aspects may implemented with respect to an NMOS transistor. Looking to
FIG. 1
a
, it illustrates a cross-sectional view of a prior art integrated circuit semiconductor device designated generally at
10
and which is built in connection with a substrate
12
. By way of example, substrate
12
is a p-type semiconductor material with an n-type well
12
′ formed in substrate
12
. Relative to n-type well
12
′ (and substrate
12
), a gate stack
14
is formed with a gate insulator
16
separating a gate
18
from n-type well
12
′. Generally, gate stack
14
is etched from a stack of layers (not shown) formed over n-type well
12
′ that include an oxide layer adjacent pntype well
12
′ and a polysilicon layer adjacent the oxide layer. Typically, when gate stack
14
is etched through those layers, most or all of the oxide layer is removed outside of the area of gate stack
14
. Thereafter, a first insulating layer
20
is formed over gate stack
14
, where first insulating layer
20
is typically oxide. Next, a p-type (e.g., boron) dopant implant is performed into device
10
. As a result, this p-type implant forms source/drain extensions
22
1
and
22
2
within n-type well
12
′ and self-aligned with respect to the thickness of insulating layer
20
where it is along the sidewalls of gate
18
.
FIG. 1
b
illustrates device
10
after the formation steps shown in
FIG. 1
a
, and additionally in
FIG. 1
b
a first anneal is performed. The annealing step activates the dopants in source/drain extensions
22
1
and
22
2
shown in
FIG. 1
a
, and this annealing thereby causes the dopants in those extensions to migrate laterally; thus, in
FIG. 1
b
, source/drain extensions
22
1
and
22
2
from
FIG. 1
a
are labeled
22
1
′ and
22
2
′ so as to distinguish them from their form prior to the anneal. Note that source/drain extensions
22
1
′ and
22
2
′ extend under gate
18
(i.e., into the transistor channel). The anneal step may be achieved using various parameters, such as a rapid thermal anneal (“RTA”) at a temperature on the order of 900° C. After the anneal, a second insulating layer
24
is formed. Typically, second insulating layer
24
is an oxide layer deposited as a conformal layer, which may be accomplished by way of example using a TEOS approach as known in the art. Such an approach commonly uses a deposition temperature on the order of 600 to 650° C. Lastly, a third insulating layer
26
is formed. Typically, third insulating layer
26
is a nitride layer, also deposited as a conformal layer. Such an approach commonly uses a deposition temperature on the order of 700 to 750° C.
FIG. 1
c
illustrates device
10
after the steps of
FIG. 1
b
, and additionally in
FIG. 1
c
an etch is performed with respect to nitride layer
26
, and insulating layers
20
and
24
; the resulting portions of these layers are labeled
26
′,
20
′, and
24
′, respectively, so as to distinguish them from their form in
FIG. 1
b
. As a result of the etch, the combination of portions
26
′,
20
′, and
24
′ form sidewall spacers along the sidewalls of gate
18
. The etch also exposes the upper surface of n-type well
12
′ beyond the area covered by the sidewall spacers and gate stack
14
. Once the sidewall spacers of
FIG. 1
c
are formed, then a p-type dopant (e.g., boron) is implanted into device
10
. This p-type implant may be achieved using various process parameters. The p-type implant forms deep source/drain regions
28
1
and
28
2
self-aligned with respect to the sidewall spacers of gate
18
.
FIG. 1
d
illustrates device
10
after the steps of
FIG. 1
c
, and additionally in
FIG. 1
d
a second anneal is performed. The second annealing step activates the dopants implanted to form deep source/drain regions
28
1
and
28
2
shown in
FIG. 1
c
. In response to the anneal, the dopants in deep source/drain regions
28
1
and
28
2
of
FIG. 1
c
midgrate laterally and they also further combine with source/drain extensions
22
1
′ and
22
2
′. For the sake of distinction, the laterally-migrated deep source/drain regions in
FIG. 1
d
are labeled
28
1
′ and
28
2
′. The second anneal step may be achieved using various parameters, such as an RTA on the order of 950 to 1100° C. and for a desirable amount of time. Lastly, following the preceding steps, various other steps may be taken to form other aspects with respect to the NMOS transistor, including other layers for connectivity and the like.
While device
10
performs adequately in many circuits and applications, it has been observed in connection with the present inventive embodiments that device
10
may provide certain drawbacks. For example, the present inventors have observed increased electrical resistance relating to the transistor channel. Such resistance undesirably reduces the transistor drive current and, thus, can be a drawback for various applications. The present inventors have therefore studied the dopant profile of source/drain extensions
22
1
′ and
22
2
′ to determine if the profile may be altered to improve the resistance characteristics of those regions and thereby improve the transistor drive current. In addition, the present inventors have examined the above-described process flow to determine if it may be improved.
In connection with a further analysis of the prior art,
FIG. 2
illustrates a plot
30
of the dopant profile for either of source/drain extensions
22
1
′ and
22
2
′ of the prior art device
10
. Plot
30
is not drawn to precise scale but instead is sketched to illustrate various aspects now described. Looking to
FIG. 2
in greater detail, its vertical axis identifies dopant concentration which begins at a zero concentration point y
0
and increases in a logarithmic fashion up the vertical axis, and its horizontal axis illustrates depth into n-type well
12
′, starting at its surface x
0
and moving into n-type well
12
′ toward the right along the horizontal axis. Generally, therefore, it may be seen from plot
30
that dopant concentration is larger toward the surface of n-type well
12
′ and then decreases at greater depths within n-type well
12
′. However, two aspects are illustrated by plot
30
that cause drawbacks and that are also

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