Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-05-11
2004-11-23
Le, Dieu-Minh (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C710S056000
Reexamination Certificate
active
06823472
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to computing systems, and more particularly to the allocation and deallocation of software resources in multiprocessor systems. More specifically, the invention relates to sharing of resources in a multiprocessor storage controller of a storage subsystem.
2. Description of Related Art
Multiprocessor systems are becoming increasingly important in modern computing since combining multiple processors increases processing bandwidth and generally improves throughput, reliability, availability and serviceability. Multiprocessor systems with dynamic allocation and deallocation of system resources (such as control blocks, access to driver routines, etc.) to and from a shared resource pool are well-known in the art. Such software resources are often stored in a shared resource pool or queue to await utilization by a processor. When a processor becomes available and issues a request, software resources are taken from the shared resource pools and transferred to the requesting processor which then utilizes the software resource. Thus, the software resources in the shared resource pool are allocated and utilized one at a time by the next requesting processor.
The pools or queues associated with these shared resources must be accessed by the multiple processors in a coordinated fashion to ensure that each processor manipulates the pools exclusive of the other processors. Such mutual exclusion techniques are well known in software techniques. Such mutual exclusion techniques impose further overhead processing load on the multiple processors of the system.
The efficiency of such systems, however, is significantly reduced by inefficient software resource management schemes. In conventional implementations, the software management routines are executed by the processors. Other software management functions are required to assure mutual exclusivity among the processors sharing the pooled resources. These software management routines require significant numbers of operations for managing queues and updating pointers and for coordinating mutually exclusive access to the shared resources. As a result, these software management routines often require a great deal of processor overhead, which in turn degrades system latency and performance. Furthermore, the processor overhead demands tend to become worse as more processors are added to the system.
These problems also arise in the context of storage systems. It is growing more common for storage subsystem controllers to utilize multiple parallel processors or control modules. Where such controllers and processors share common resources, similar allocation and coordination techniques are applicable. The overhead processing load on the processors of such multiprocessor storage controllers can negatively impact storage subsystem performance.
For example, the I
2
O interface standard defines a layered model for software interface modules between a computer software application and an I/O interface device. The layers of the model communicate in accordance with application program interfaces (APIs) defined by the specification. A message frame is a fundamental unit of information exchanged between certain of the layers. A message frame address (MFA) is a pointer to one such message frame. A pool of such message frames is maintained in the I
2
O compliant interface memory. The standard suggests a free list and a post list of MFAs. Each MFA points to one message frame in the pool. Initially all MFAs are on the free list. When a processor requires a message frame for messaging purposes between the layers of the I/O interface, it allocates a next available MFA from the free list. To pass the message to a receiving layer, the message is placed on a post list. A receiving processor then retrieves a next posted MFA from the post list. The message pointed to by the retrieved MFA is processed as appropriate for the messaging application. When the message processing is completed, the MFA is stored back on the free list for further use by another process (or processor).
In addition to management of the lists per se, the processors must also coordinate the mutually exclusive access to the lists. Such mutual exclusion operations consume still further overhead of the processors.
MFA management is but one example of a shared resource pertinent to I
2
O applications. A wide variety of such software resource are common in the context of storage controllers having multiple processors (i.e., multiple redundant controllers). For example, other common shared resources may include: cache control blocks, recovery control blocks, I/O control structures, scatter/gather list elements, etc.
Further, the problems described above are compounded where multiple such resource must be managed among a plurality of processors. The overhead processing within each of the multiple processors associated with managing a single such shared resource are simply multiplied when managing additional such shared resources.
Accordingly, a need exists for a shared resource management technique in a multiprocessor system that reduces demands on processor overhead and improves system performance.
SUMMARY OF THE INVENTION
The present invention solves the above and other problems, and thereby advances the useful arts, by providing a shared resource manager assist circuit designed to provide assistance to the processors to manage such shared resources and the coordination of mutually exclusive access to the shared resources. Preferably, the shared resource manager is embodied in an integrated circuit chip separate from the processors. The shared resource manager allocates and deallocates software resources for utilization by the processors in response to allocation and deallocation requests by the processors, thereby providing rapid and efficient management of the software resources and improving overall system performance. The standard bus interface of the custom chip provides the mutual exclusivity required for management of a shared resource by multiple processors connected to the manager chip's interface bus.
Generally speaking, the shared resource manager includes a bus arbitrator for interfacing with a system bus coupled to the processors, a memory block with resource control blocks that point to resources stored in a memory, and an allocation/deallocation means that manages a list of available resources.
The present invention is applicable to a wide variety of applications where software resources are shared among a plurality of processors. In one exemplary embodiment, the resource control blocks are message frame address values (MFAs) compliant with
120
specifications. MFA management is exemplary of one such software resource potentially shared among a plurality of processors in an I/O adapter environment having multiple processors performing I/O request processing. Examples of other typical software resources in the context of storage controllers include: cache control blocks, recovery control blocks (“RCB”), I/O control structures, DMA scatter/gather list elements, etc.
An allocation request is processed by the present invention by retrieving the next available RCB on the list being managed. Conversely, a deallocation request puts the RCB provided back on the list as an available RCB. In the I
2
O exemplary embodiment, the free list and post list would be shared managed resources. Each list is managed as a FIFO stack. In reference to the free list, allocations are referred to as “allocates” while deallocation requests are referred to as “releases.”
In particular, the shared resource manager of the present invention is useful where a number of shared resources are managed among the multiple processors. One shared resource manager is allocated for each such shared resource. The assistance provided by such multiple shared resource manager devices in a multiple processor application as dramatically reduces the overhead processing load imposed on the multiple processors.
It is therefore an object of the
DeKoning Rodney A.
Gates Dennis
Holt Keith
Kloeppner John
Duft Setter Ollila & Bornsen LLC
Le Dieu-Minh
LSI Logic Corporation
LandOfFree
Shared resource manager for multiprocessor computer system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Shared resource manager for multiprocessor computer system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Shared resource manager for multiprocessor computer system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3363425