Method of designing interconnects

Details Method of designing interconnects Method of designing interconnects

2003-05-19

2004-11-09

Whitmore, Stacy A. (Department: 2812)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C324S719000

Reexamination Certificate

active

06816995

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of designing interconnects, and more particularly to a method of designing interconnect for semiconductor devices having a multilayer interconnect structure that employs copper (Cu) as an interconnect material.
2. Description of the Related Art
There has heretofore been known a method of forming metal interconnect in semiconductor devices such as LSI (Large Scale Integrated) circuits.
While aluminum (Al) has been used as a major interconnect material, Cu has recently found a growing use as another interconnect material in order to decrease interconnect resistivity and increase migration resistance for higher device performance.
For forming Cu interconnect, the damascene technology is widely used because it would be difficult to etch thin films of Cu that have been formed. The damascene process is a process of forming Cu interconnects by embedding Cu in grooves according to a film growing process such as plating or the like and thereafter using the chemical mechanical polishing to remove excessive Cu therefrom. The damascene process is divided into a single damascene process and a dual damascene process. According to the single damascene process, metals for making up vias is embedded before interconnects are formed.
For producing interconnect according to the damascene technology, it is necessary to provide a barrier metal for preventing embedded Cu from being diffused into interlayer dielectrics. Since the barrier metal is present in an interconnect region that is held in contact with a via, a material continuity is lost in the interconnect region that contacts the via.
When current flows through a metal interconnect in an LSI circuit, an electromigration in which metal atoms move interconnect stresses in the direction of the electron flow occurs there. A large number of holes that are accumulated upstream in the electron flow become physical holes that can optically be observed, i.e., a void. The metal atoms existing at any position move interconnect stresses in the direction of the electron flow. Since the barrier metal is present in an interconnect region that is joined to a via and metal atoms cannot penetrate the barrier metal, the metal atoms only move in the interconnect region joined to the via, and no fresh metal atoms are supplied to the interconnect region joined to the via. Therefore, holes from which the metal atoms have moved, i.e., a void, are liable to be formed in the interconnect region joined to the via.
Interconnects where a void produced by the movement of metal atoms has grown to a certain size is rendered electrically nonconductive or has its resistance increased, presenting signal transmission difficulties. Therefore, it has been customary at the time of designing an LSI circuit to produce an interconnect life predicting formula for allowing interconnect to transmit signals without being adversely affected by voids within a desired period of actual use. An LSI interconnect life that is predicted based on the interconnect life predicting formula has posed a limitation on the designing of LSI circuits. The interconnect life predicting formula for interconnect has been produced uniformly based on the characteristics of an interconnect structure whose life is shortest. Consequently, an interconnect structure that is less liable to generate voids and hence is expected to have a longer life is given an excessive limitation on an allowable current value therefore. Stated otherwise, an interconnect life cannot accurately be recognized because no consideration has been given to the fact that an interconnect life is varied depending on whether voids are easily generated or not. Certain interconnect structures are thus subject to unnecessary allowable current limitations, which prevent semiconductor devices from being designed for higher-speed operation.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of designing interconnects without posing unnecessary allowable current limitations thereon by accurately recognizing an interconnect life in view of the fact that an interconnect life is varied depending on whether voids are easily generated or not.
To accomplish the above object, there is provided a method of designing an interconnect of a semiconductor device having a multilayer interconnect structure, comprising the steps of predicting the life of the interconnect governed by an electromigration with different predicting models that are classified according to a void incubation period and a void growth period of a void that occurs in the vicinity of a junction between the interconnect and a via which connects upper and lower interconnect, and designing the interconnect based on the predicted life.
According to the above method, the life of an interconnect governed by an electromigration is predicted with different predicting models that are classified according to a void incubation period and a void growth period of a void that occurs in the vicinity of a junction between the interconnect and a via which connects upper and lower interconnect, and the interconnect of a semiconductor device having a multilayer interconnect structure is designed based on the predicted life. Therefore, the life of the interconnect can accurately be recognized in view of different interconnect lives depending on whether a void can easily be formed or not, and the interconnect can be designed without unduly limiting an allowable current therefore.
Furthermore, there is also provided in accordance with the present invention a method of checking an interconnect when the interconnect is designed by the above method of designing the interconnect.
The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate an example of the present invention.


REFERENCES:
patent: 5581475 (1996-12-01), Majors
patent: 5963729 (1999-10-01), Aji et al.
patent: 6010962 (2000-01-01), Liu et al.
patent: 6532570 (2003-03-01), Mau
patent: 6578178 (2003-06-01), Mau
patent: 6603321 (2003-08-01), Filippi et al.
patent: 6634013 (2003-10-01), Shinzawa
patent: 2003/0080761 (2003-05-01), Filippi et al.
patent: 4-340739 (1999-05-01), None
patent: 2000-3947 (2000-01-01), None
patent: 2000-058544 (2000-02-01), None
Gan, C.L., et al., “Contrasting failure characteristics of different levels of dual-damascene metallization”, IEEE. 7/02. pp. 124-128.

Affiliated with

Also associated with

Rating

Method of designing interconnects does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of designing interconnects, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of designing interconnects will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3362202