Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output command process
Reexamination Certificate
2001-09-28
2004-06-08
Huynh, Kim (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output command process
C710S036000, C710S050000
Reexamination Certificate
active
06748460
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to communications between processes in a multiprocessor system, and more particularly relates to implementing initiative passing in an input/output (I/O) operation without interrupt overhead.
BACKGROUND OF THE INVENTION
U.S. Pat. No. 4,447,873 issued May 8, 1984 to Price et al. for INPUT-OUTPUT BUFFERS FOR A DIGITAL SIGNAL PROCESSING SYSTEM discloses buffer interfaces wherein a storage controller which generates control signals indicating when it is condition to receive a vector of data words from the storage controller, whereon the storage controller transfers a vector of data to the input buffer.
U.S. Pat. No. 5,671,365 issued Sep. 23, 1997 to Binford et al. for I/O SYSTEM FOR REDUCING MAIN PROCESSOR OVERHEAD IN INITIATING I/O REQUESTS AND SERVICING I/O COMPLETION EVENTS, and U.S. Pat. No. 5,875,343 issued Feb. 23, 1999 to Binford et al. for EMPLOYING REQUEST QUEUES AND COMPLETION QUEUES BETWEEN MAIN PROCESSORS AND I/O PROCESSORS WHEREIN A MAIN PROCESSOR IS INTERRUPTED WHEN A CERTAIN NUMBER OF COMPLETION MESSAGE ARE PRESENT IN ITS COMPLETION QUEUE disclose an apparatus wherein I/O requests are queued in a memory shared by one or more main processing units and one or more I/O processors. Each I/O processor is associated with a queue, and each main processing unit is associated with a queue shared with the I/O processors. Each I/O processor may continue processing queued I/O requests after completing processing an earlier request. A threshold value indicates the minimum number of completed I/O requests required before an interrupt request is generated to the main processing unit. Many events are batched together under one interruption.
U.S. Pat. No. 5,771,387 issued Jun. 23, 1998 to Young et al. for METHOD AND APPARATUS FOR INTERRUPTING A PROCESSOR BY A PCI PERIPHERAL ACROSS AN HIERARCHY OF PCI BUSES discloses a hierarchy of PCI buses for facilitating PCI agents coupled to the lower lever PCI buses to interrupt a processor during operation.
U.S. Pat. No. 6,032,217 issued Feb. 29, 2000 to Arnott for METHOD FOR RECONFIGURING CONTAINERS WITHOUT SHUTTING DOWN THE SYSTEM AND WITH MINIMAL INTERRUPTION TO ON-LINE PROCESSING discloses a method for concurrently reorganizing a disk file system while continuing to process I/O requests. The method includes stopping processing of new I/O requests by queuing them within the system, finishing processing I/O requests in progress, performing the reorganization, and then processing the queue of stored I/O requests before finally resuming normal operation.
U.S. Pat. No. 6,085,277 issued Jul. 4, 2000 to Nordstrom et al. for INTERRUPT AND MESSAGE BATCHING APPARATUS AND METHOD discloses an interrupt and batching apparatus for batching interrupt processing for many events together.
SUMMARY OF THE INVENTION
The present invention includes an apparatus, method and program product for use in passing initiative to a processor for handling an I/O request for an I/O operation for sending data between a main storage and one or more devices, as defined herein. A hierarchy of vectors registers I/O requests by the devices to send or receive data from the main storage. The hierarchy of vectors has one or more lower levels and a highest level. Each device is assigned to a vector in the lowest level of the hierarchy for registering an I/O request, the setting of a vector in the lowest level being reflected up the hierarchy to the highest level, thereby registering I/O requests on any lower level of the hierarchy in the highest level. A software function referred to herein as the dispatcher polls the hierarchy in high to low order with the dispatcher passing initiative to the processor to handle I/O requests registered in said hierarchy responsive to registering of an I/O request on the lowest level as reflected to the highest level of said hierarchy.
The present invention provides implementation of low overhead I/O initiative passing that is scaled both vertically with the types of devices, and horizontally with the number of devices in a given type.
An object of the present invention is that no interrupt overhead is required to inform the processor that an I/O operation has completed. Instead the dispatcher polls completion vectors when it is convenient during its dispatch cycle. Thus, system overhead, such as that caused by cache corruption, can thereby be avoided.
Another object of the present invention is that large numbers of devices can be supported efficiently by implementing a multi-tier hierarchy in the completion vectors. This structure allows both vertical scaling (all devices are managed by a single operating system (OS) image), and horizontal scaling (a single host provides separate virtual environments, with each having their own OS image).
Another object of the present invention that, since each device has its own byte within a completion vector, no serialization among the devices is necessary to inform the processor of I/O completion events. This is a significant improvement over the current S/390 subchannel interrupt generation activity that requires serialization to add/remove elements from queues as part of interrupt generation/consumption.
Another object of the present invention is to provide a design that is extremely flexible in that new, yet to be defined, devices can easily be mapped into this model.
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Brice, Jr. Frank W.
Glassen Steven G.
Schmidt Donald W.
Yudenfriend Harry M.
Gonzalez Floyd A.
Huynh Kim
International Business Machines - Corporation
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