Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2003-01-17
2004-06-01
Prenty, Mark (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S773000, C324S765010
Reexamination Certificate
active
06744067
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor testing and, more particularly, to wafer-level burn-in and testing of components on semiconductor wafers.
2. State of the Art
It is advantageous in semiconductor processing to detect and screen out defective integrated circuits (ICs) as early as possible in the manufacturing process. It is appreciated that many manufactured ICs fail within the first few months or weeks of use due to processing defects. Such a defect profile is commonly known as “infant mortality” and is clearly very undesirable and unacceptable for a typical IC customer. To discover those circuits that are susceptible to infant mortality, manufacturing processes have included high temperature testing of ICs for extended periods of time before shipping products to a customer.
In a typical semiconductor manufacturing process, a multiplicity of integrated circuits is formed as individual dice on a semiconductor wafer. Such a multiplicity of integrated circuits may number in the tens to hundreds, or even thousands (such as in a 300 mm wafer) of individual dice which are generally repeated across the wafer in a two-dimensional array. Once the dice are formed on a semiconductor wafer, the dice are then tested to determine which dice are functional with such a determination performed, generally, by probing each die individually. The probing of individual dice is performed using very costly probe equipment while the die is still in wafer form. Presently available probe equipment contacts each bonding pad on an individual die with a separate probe. A typical probe test requires that each die is probed in order to determine the correct and acceptable functionality of each die. However, due to the expensive nature of the probing test equipment, reliability testing (i.e., testing an individual circuit over time) is generally not performed.
It should be apparent that the purpose of wafer-level probing is to determine as early as possible in the manufacturing process the functional nature of each individual die. The earlier a defective die is detected, the fewer subsequent processing steps are formed on the defective die, which results in a reduction of costs associated with individual wafer processing.
Upon the completion of functional probe testing, those detective dice are noted and subsequent manufacturing processes are not exerted.
Upon the identification of functional and nonfunctional dice, the dice are then separated or singulated by way of a dicing process. Following singulation, functional dice are packaged into integrated circuit packages or undergo further processing which allows the dice to be assembled as part of a higher-level assembly, which itself may be packaged. Once the dice have been packaged or prepared for packaging within a higher assembly, thorough electrical testing is performed to determine whether each packaged integrated circuit properly performs the functionality for which it was designed. Upon successful package testing, integrated circuits may be sold or integrated into higher assemblies.
An additional common manufacturing process includes subjecting the packaged integrated circuits to a form of reliability testing called burn-in. Burn-in testing involves testing an IC for an extended period of time at elevated operational temperatures. During the burn-in test, additional infant mortality failures manifest themselves and are further culled from the original multiplicity of manufactured dice. Burn-in testing may also utilize reduced temperature testing and may further include repetitive cycling of the packaged integrated circuit in an attempt to fatigue and fail frail ICs. Typical burn-in testing has utilized a concept of burning in packaged dice which have less fine-pitched inputs and outputs. Furthermore, the inputs and outputs of the packaged integrated circuit provide a more economical testing approach rather than the very fine-pitched probing mechanism used for individual die probing.
Conventional economical and high-volume approaches for burn-in testing of dice at a wafer level have required expensive and customized probing equipment. Therefore, there exists a need for a wafer-level testing methodology that does not require special processing or elaborate probe testing of individual integrated circuits at a wafer-level burn-in stage.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, semiconductor components configured for wafer-level testing, semiconductor wafers fabricated for wafer-level testing and methods for fabricating wafer-level testable dice are provided.
A semiconductor component includes a semiconductor die that performs specific functions and contains circuitry for performing those specific functions. The semiconductor die is fabricated according to conventional fabrication processes with each die including a defined number of die contacts that are electrically exposed for subsequent interconnection with other electronic components. One embodiment of the present invention contemplates busing contacts of interest together from at least one die to at least one other die for wafer-level testing.
In addition to at least one die, the semiconductor component includes a redistributed circuit for electrically coupling the die contact on the semiconductor die to a redistributed contact such as a bumped contact. The redistribution circuit is formed on top of the conventionally processed semiconductor wafer with the conductive trace electrically coupling with the die contact. The conductive trace is preferably formed by patterning a conductor such as aluminum onto the exposed wafer surface. The redistribution circuit may or may not physically contain the solder ball portion of the bumped contact; however, in one topology, the redistribution circuit's patterned conductor may serve as an isolation region for forming an open circuit therein when a die is determined to be nonfunctional.
The semiconductor component configured for wafer-level testing also includes a bus conductor for providing a die-to-die routing of a specific signal. The specific signal is then available to test equipment at the wafer level for providing inputs or for receiving outputs. The bus conductor traverses at least a portion of the semiconductor die for providing the die-to-die interconnection or busing function. The bus conductor may also be formed from patterned conductors and is preferably formed in the same processes that form the patterned conductor used in the redistribution layer.
The bus conductor is also in electrical communication with the redistribution circuit to receive or provide a signal to the die contact of the specific die. To facilitate the electrical connection between the bus conductor and the redistribution circuit, various embodiments are presented. One embodiment contemplates the intersection of the bus conductor and the redistribution circuit, while another embodiment forms an additional conductor for providing the electrical coupling. As with the bus conductor, this conductor may be formed in a unitary process with both the distribution circuit and the bus conductor.
While not all dice on a wafer may he functional and cooperative for wafer-level testing, the present invention contemplates probe testing the dice on a wafer that have been manufactured with the wafer-level testable circuitry of the present invention. Functional and nonfunctional dice are identified with location information stored that is used in a follow-up process that isolates the nonfunctional dice from the networked configuration of the dice on the wafer. In order to remove or isolate the nonfunctional dice from the wafer-level test grid, one or more die contacts from the nonfunctional wafer are isolated from the respective bus conductor. The isolation process may take the form of removing any outer passivation layer that exists over the redistribution circuit region or the conductor that connects the redistribution circuit to the bus conductor to expose the underlying conductive trac
Farnworth Warren M.
McDonald Steven M.
Prenty Mark
TraskBritt
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