Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2001-07-13
2004-08-17
Padmanabhan, Mano (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S217000, C711S167000, C710S035000
Reexamination Certificate
active
06779074
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to memory devices and, more particularly, to methods and circuits for reading information out of and writing information into the memory device.
2. Description of the Background
Computer designers are continually searching for faster memory devices that will permit the design of faster computers. A significant limitation on a computer's operating speed is the time required to transfer data between a processor and a memory circuit, such as a read or write data transfer. Memory devices such as dynamic random access memories (DRAMs), synchronous dynamic random access memories (SDRAMs), flash memories, etc. typically include a large number of memory cells arranged in one or more arrays, each array comprised of rows and columns. Each memory cell provides a location at which the processor can store and retrieve one bit of data, sometimes referred to as a memory bit or mbit. The more quickly the processor can access the data within the memory cells, the more quickly it can perform a calculation or execute a program using the data.
FIG. 1
shows, in part, a typical computer system architecture. A central processing unit (CPU) or processor
10
is connected to a processor bus
12
, which in turn is connected to a system or memory controller
14
. The memory controller
14
may be connected to an expansion bus
16
. The memory controller
14
serves as interface circuitry between the processor
10
and a memory device
18
. The processor
10
issues a command and an address which are received and translated by the memory controller
14
. The memory controller
14
applies the translated command signals on a plurality of command lines
20
and the translated address on a plurality of address lines
22
to the memory device
18
. These command signals are well known in the art and include, in the case of a DRAM, RAS (row address strobe), CAS (column address strobe), WE (write enable) and OE (output enable). A clock signal is also provided on CLK lines
24
. Corresponding to the processor-issued command and address, data is transferred between the controller
14
and the memory
18
via datapath lines
26
.
The memory
18
typically comprises a number of memory ranks
27
, a representative one of which is illustrated in FIG.
2
. In this example, the memory rank
27
is configured for a 64-bit system, having eight 8-bit memory circuits
28
(
0
)-
28
(
7
). The command signals RAS, CAS and WE are applied to all memory circuits
28
(
0
)-
28
(
7
) in the rank
27
. In a memory
18
(
FIG. 1
) having additional ranks, separate CS command signals would be provided for each rank. Hence, the command signal CS is often referred to as a rank-specific command signal. The address bus
22
is connected to all the memory circuits
28
(
0
)-
28
(
7
) in the rank
27
and to all other memory circuits (not shown) in all other ranks (not shown) of the memory
18
. Hence, the address bus
22
is often referred to as globally connected.
A synchronous DRAM (SDRAM) is a memory device capable of sequentially accessing, by virtue of internal operations, a certain range of addresses at high speeds. In a typical SDRAM, a read/write rate of 100 Mbytes/sec or greater is possible. To achieve such speeds, the read/write of an SDRAM is performed in a burst mode. Burst mode is a mode of address access where data having the same row addresses are read or written continuously in blocks of 2, 4, or 8 bit words. In addition, the access for such words in the block is made by simply providing the start address of the block. Afterward, the remaining addresses are generated automatically in the SDRAM in accordance with its mode of operation: sequential or interleave. The mode of operation is determined by an address sequence from the CPU. Addresses for each burst address sequence method are generated, in the sequential mode, by addition of the burst start address and an output of an internal counter. In the interleave mode, the addresses are generated by an exclusive OR of the burst start address and an output of an internal counter. The same wrap mode is used for both read and write operations, with all column address bits used for both read and write operations.
As clock speeds increased above 200 MHz (i.e. RDRAM or SLDRAM), the core operation of the DRAM did not increase at the same rate. Therefore, the DRAMs completed the reads and writes on 4 or 8 words internally and then output the word sequentially onto the external bus. As entire groups of data words were being transferred, the least significant column addresses were no longer transmitted to the DRAM.
That solution works well for write data from a controller to the DRAM as it can be aligned to a cache fill. However, because a complete block of data words is transferred at the same time for reads, the most critical word is not always received first by the controller, which can add latency to the system. The need exists for a high clock rate DRAM memory supporting the block transfers of data words while delivering the most critical word first to the controller. Additional need exists for a communication protocol between the memory controller and the DRAM to support such a new feature.
SUMMARY OF THE PRESENT INVENTION
The present invention is an addressing scheme and associated hardware to allow for two different types of access, one for reading and one for writing, to take place. A memory device constructed according to the invention comprises a plurality of arrays of memory cells. Peripheral devices are provided for reading information out of and for writing information into the plurality of memory cells, including:
a reorder circuit responsive to certain address bits for ordering bits received from the plurality of arrays; and
an address sequencer for routing certain of the address bits to the reorder circuit during a read operation.
The method of the present invention comprises reordering a block of n-bit words output from a memory array according to information in certain address bits before outputting at least one n-bit word from a memory device. In an exemplary embodiment, the method is for accessing a DRAM and is comprised of the following: using the values on the bank address inputs to select an array bank;
using the column address provided on inputs A
3
-Ai, where i is the most significant column address;
using the column address provided on inputs A
0
-A
2
to identify a burst order for a read access; and
ignoring the column address provided on inputs A
0
-A
2
during a write access. Thus, for reads a specific 8 bit burst is identified by the most significant column address bits while the least significant bits CA
0
-CA
2
identify the most critical word and the read wrap sequence after the critical word. For writes, the burst is identified by the most significant column addresses with CA
0
-CA
2
being “don't care” bits assumed to be 000. Other Implementation schemes are possible
An important feature that results from having a read access that differs from the write access is that reads are carried out in a manner so that the critical word is available to the memory controller such that an interleaved burst mode is supported. Writes, on the other hand, can be simplified based on a start sequential burst as the write data may be generated from data held in cache. The present invention supports improved latency for the system by providing the memory controller with the critical word first. Also, the system does not have to reorder the column address bits between read and write commands. Those, and other advantages and benefits, will be apparent from the Description of the Preferred Embodiments appearing hereinbelow.
REFERENCES:
patent: 5749086 (1998-05-01), Ryan
patent: 5784705 (1998-07-01), Leung
patent: 5850368 (1998-12-01), Ong et al.
patent: 5903496 (1999-05-01), Kendall et al.
patent: 5917760 (1999-06-01), Millar
patent: 5940875 (1999-08-01), Inagaki et al.
patent: 5966724 (1999-10-01), Ryan
patent: 6640266 (2003-10-01), Arcoleo et al.
Micro)n Technology, Inc.
Namazi Mehdi
Padmanabhan Mano
Thorp Reed & Armstrong LLP
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