Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

2002-03-13

2004-06-29

Zarabian, Amir (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S316000, C257S314000

Reexamination Certificate

active

06756630

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory devices and manufacturing methods thereof.
2. Description of the Background Art
A nonvolatile semiconductor memory device according to a conventional art and a method of manufacturing the nonvolatile semiconductor memory device are described below in conjunction with
FIGS. 9A-9D
to
FIGS. 21A-21D
and
FIGS. 22-24
. The nonvolatile semiconductor memory device includes two regions, i.e., a memory cell region and a peripheral circuitry region. In
FIGS. 9A-9D
to
FIGS. 21A-21D
, “A” and “B” (e.g.
FIGS. 9A and 9B
,
10
A and
10
B . . . ) represent the peripheral circuitry region and “C” and “D” (e.g.
FIGS. 9C and 9D
,
10
C and
10
D . . . ) represent the memory cell region. Further, “A” (e.g.
FIGS. 9A
,
10
A . . . ) represents an NMOS transistor region
200
and “B” (e.g.
FIGS. 9B
,
10
B . . . ) represents a PMOS transistor region
100
that are included in the peripheral circuitry region. A cross section in parallel with word lines of the memory cell region is represented by “C” (shown in
FIGS. 9C
,
10
C . . . ) and a cross section in parallel with bit lines thereof is represented by “D” (shown in
FIGS. 9D
,
10
D . . . ).
Referring to
FIGS. 9A-9D
, an isolation oxide film
2
is formed at a main surface of a silicon substrate
1
. A resist (not shown) is formed on the entire main surface of silicon substrate
1
. Apart of the resist that is formed on PMOS transistor region
100
is removed. The remaining resist is used as a mask to carry out ion implantation under the conditions of 1.2 MeV and 1.0×10
13
cm
−2
, for example, for implanting phosphorus as impurities and thus form an N well
3
. Further, phosphorus ions are implanted for channel cutting of isolation oxide film
2
under the conditions of 700 keV and 3.0×10
12
cm
−2
for example, and boron ions are implanted for channel doping of the surface layer under the conditions of 20 keV and 1.5×10
12
cm
−2
for example. The resist is then removed to obtain N well
3
in PMOS transistor region
100
as shown in
FIGS. 10A-10D
.
A resist (not shown) is formed on the entire main surface of silicon substrate
1
. A part of the resist that is formed on NMOS transistor region
200
and the memory cell region is removed. The remaining resist is used as a mask to carry out ion implantation under the conditions of 700 keV and 1.0×10
13
cm
−2
, for example, for implanting boron as impurities and thus form a P well
4
. Further, boron ions are implanted for channel cutting of isolation oxide film
2
under the conditions of 270 keV and 3.5×10
12
cm
−2
for example, and boron ions are also implanted for channel doping of the surface layer under the conditions of 50 keV and 1.2×10
12
cm
−2
for example. The resist is thereafter removed to obtain P well
4
in NMOS transistor region
200
and the memory cell region as shown in
FIGS. 11A-11D
.
On the entire exposed part of the main surface of silicon substrate
1
, a silicon oxide film
5
is formed to a thickness of 100 Å by thermal oxidation. Silicon oxide film
5
is to be used as a tunnel oxide film. A phosphorus-doped polycrystalline silicon layer
6
is further formed to cover the upper side of silicon oxide film
5
to a thickness of 1000 Å by low-pressure CVD (Chemical Vapor Deposition) for the polycrystalline silicon film. By means of photolithography, a predetermined patterning process is conducted to etch phosphorus-doped polycrystalline silicon layer
6
of the memory cell region. After this etching, silicon oxide film
5
and phosphorus-doped polycrystalline silicon layer
6
of the peripheral circuitry region are left as they are. Then, by means of ion implantation, arsenic ions are implanted under the conditions of 40 keV and 2×10
15
cm
−2
for example to form n-type diffusion layers
7
a
and
7
b
in the memory cell region. In this way, the structure as shown in
FIGS. 12A-12D
is completed.
A silicon oxide film of 50 Å in thickness by thermal oxidation, a silicon nitride film of 100 Å in thickness by low-pressure CVD and a silicon oxide film of 50 Å in thickness by low-pressure CVD are formed in this order and accordingly, a three-layer insulating film
8
(also referred to as “ONO film”) is produced. The structure as shown in
FIGS. 13A-13D
is thus completed.
By means of photolithography, a resist is formed to partially cover the memory cell region, and three-layer insulating film
8
, phosphorus-doped polycrystalline silicon layer
6
and silicon oxide film
5
in the peripheral circuitry region are removed. Then, the structure as shown in
FIGS. 14A-14D
is completed.
Thermal oxidation is used to grow a silicon oxide film
9
to a thickness of 150 Å, that is to be used as a gate electrode of a transistor of the peripheral circuitry region. In the memory cell region at this stage, the silicon nitride film of three-layer insulating film
8
prevents underlying phosphorus-doped polycrystalline silicon layer
6
from being thermally oxidized. Then, by means of low-pressure CVD, a phosphorus-doped polycrystalline silicon layer
10
of 2000 Å in thickness and a silicon oxide film
11
of 2000 Å in thickness are deposited. A resist with a desired pattern is formed by photolithography, and this resist is used as a mask to pattern silicon oxide film
11
. After removal of this resist, silicon oxide film
11
is used as a mask to pattern phosphorus-doped polycrystalline silicon layer
10
that is to be used as a gate electrode of a transistor of the peripheral circuitry region. Simultaneously, phosphorous-doped polycrystalline silicon layer
10
is also patterned that is to be used as a control electrode of a transistor of the memory cell region. In this way, the structure as shown in
FIGS. 15A-15D
is completed.
A resist is formed to cover the peripheral circuitry region, and silicon oxide film
11
of the memory cell region is used as a mask to etch three-layer insulating film
8
and phosphorus-doped polycrystalline silicon layer
6
and accordingly form a floating gate electrode of a transistor of the memory cell region. The structure as shown in
FIGS. 16A-16D
is accordingly completed.
A resist is further formed by photolithography to cover PMOS transistor region
100
and the memory cell region. The resist is used as a mask to implant phosphorus ions of 2×10
13
cm
−2
with 70 keV energy. Consequently, a low-concentration n-type diffusion layer
12
of an N channel transistor is formed in NMOS transistor region
200
. The resist is thereafter removed and the structure as shown in
FIGS. 17A-17D
is completed.
By photolithography, a resist is formed to cover NMOS transistor region
200
and the memory cell region. The resist is used as a mask to implant BF
2
ions of 7×10
12
cm
−2
with 70 keV energy. As a result, a low-concentration p-type diffusion layer
13
of a P channel transistor is formed in PMOS transistor region
100
. The resist is then removed and the structure as shown in
FIGS. 18A-18D
is completed.
By CVD, a silicon oxide film is deposited to a thickness of 2000 Å. Anisotropic etching of this silicon oxide film produces a sidewall spacer
14
. By photolithography, a resist is formed to cover PMOS transistor region
100
and the memory cell region. This resist is used as a mask to implant arsenic ions of 3×10
15
cm
−2
with 50 keV energy. The resist is then removed. By photolithography again, a resist is formed to cover NMOS transistor region
200
and the memory cell region. The resist is used as a mask to implant BF
2
ions of 3×10
15
cm
−2
with 30 keV energy. The resist is removed and thus the structure shown in
FIGS. 19A-19D
is completed. In this structure, a high-concentration n-type diffusion layer
15
of the N channel transistor and a high-concentration p-type diffusion layer
16
of the P channel transistor are formed

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