Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-04-30
2004-08-31
Guerrero, Maria (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S585000, C438S592000, C438S642000, C438S652000, C438S655000, C438S682000, C438S692000
Reexamination Certificate
active
06784098
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of performing the process of salicidation.
(2) Description of the Prior Art
The continuing trend in the semiconductor industry for device performance improvements has resulted over the years in dramatically reducing devices features and device interconnect lengths and in increasing device packaging density. One type of semiconductor device on which this trend has had a major impact is the Field Effect Transistor (FET), which has found extensive application in the era of Ultra Large Scale Integration (ULSI) of semiconductor devices.
FET devices are typically created over an active surface region of a silicon substrate by first growing a thin layer of gate oxide, which serves as a stress relieve layer between the FET device and the underlying silicon substrate. A layer of typically polysilicon is deposited over the layer of gate oxide and patterned to form the body of the gate electrode that is an integral part of the FET. Impurity implants are then performed into the surface of the underlying silicon substrate, which are self-aligned with the gate electrode of the FET, to determine the conductivity of the surface of the substrate and therewith the performance characteristics of the FET. These impurity implants are known as Lightly Doped Diffusions (LDD) and the implants for the source and drain regions of the FET. Gate spacers are typically formed on the sidewalls of gate electrode, the source and drain implants are in this case performed after the gate spacers have been created.
With continued miniaturization of the FET, the channel length of the FET, which is the distance between the source and the drain region of the gate electrode as measured along the surface of the substrate, continues to decrease in value to where this value approaches 0.25 &mgr;m.
With the overall scaling down of the FET supporting elements, such as the source/drain implants of the FET, must also be proportionally reduced. The FET is interconnected to surrounding circuitry by establishing electrical contacts with the source/drain regions of the gate electrode and with the surface of the layer of polysilicon that forms the body of the gate electrode. With reduced device dimensions and the therewith reduced depth of implant of the source/drain impurities, it stands to reason that the surface contact that is established with the source/drain regions becomes relatively more important. Specifically, this surface contact must be a low resistivity contact in order to avoid a negative impact on device performance. This low resistivity can be established by forming a thin silicide layer over the surface of the source/drain regions and the surface of the layer of polysilicon of the FET device, using a process that is known as salicidation. The method of self-aligned silicide (salicide) formation, which self-registers with the contacts at the top of the polysilicon gate, the source and the drain, helps solve the problem of critical dimension tolerance.
For advanced FET devices, which have a channel length of 0.25 &mgr;m or less, it is difficult for the conventional process of salicidation to simultaneously meet the requirements of ultra shallow junction depth and of low sheet resistivity of the surface of the contact regions. Junction leakage can be reduced by reducing the thickness of the layer of silicide, this however increases the sheet resistivity. The invention provides a method that addresses these concerns.
U.S. Pat. No. 6,140,216 (Richart et al.) shows a silicide S/D CMP to expose gate and Silicide gate top.
U.S. Pat. No. 5,731,239 (Wong et al.), U.S. Pat. No. 6,177,366 (Lin et al.), U.S. Pat. No. 6,162,691 (Huang), U.S. Pat. No. 6,146,994 (Hwang) and U.S. Pat. No. 6,153,485 (Pey et al.) show related silicide processes.
SUMMARY OF THE INVENTION
A principle objective of the invention is to provide a method of salicidation whereby uniform polishing of the salicided surfaces is maintained.
Another objective of the invention is to provide a method of salicidation whereby endpoint detection of polishing of the salicided surfaces does not present a problem.
Yet another objective of the invention is to provide a method of salicidation whereby polishing of the salicided surface can be performed using relatively relaxed parameters of polishing time, that is providing a relatively wide “processing window” for the polishing operation.
In accordance with the objectives of the invention a new method is provided for forming salicided surfaces to a FET device. Gate electrodes are formed, including the formation of silicon oxide gate spacers and the source/drain region implants. The gate electrode consists, for the first embodiment of the invention, of stacked layers of silicon oxide (pad oxide), polysilicon and boronitride (BN). A thin layer of Ti/TiN is deposited, a low temperature anneal is performed creating salicided surfaces of the source/drain regions. A selective wet etch removes unreacted Ti/TiN, a thin layer of silicon oxide is deposited (liner oxide). A thick layer of photoresist, filling the spaces between the gate electrodes and extending above the upper layer of BN of the gate electrodes. The layer of photoresist is polished, stopping on the layer of BN, the surface of the layer of BN is now exposed, the layer of BN is removed. A thick layer of Ti/TiN is next deposited, filling the opening from where the layer of BN has been removed. A low temperature anneal anneals the layer of Ti/TiN with the underlying polysilicon of the gate electrode, forming TiSi
x
in the region where the layer of Ti/TiN is in contact with the polysilicon of the gate electrode. The unreacted Ti/TiN is removed with a selective wet etch, leaving the layer of thick TiSi
x
in place overlying the gate electrode. A high temperature anneal is applied to reduce the sheet resistance of the layer of TiSi
x
.
As an alternate approach to the above cited sequence, forming the second embodiment of the invention, the function of the layer of photoresist can be replaced with a layer of boro-phosphate-silicate-glass (BPSG), the function of the top layer of BN can be replaced with a layer of silicon nitride.
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Stanley Wolf “Silicon Processing for the VLSI Era”, 1990, vol. 2, pp. 143-150.
Ackerman Stephen B.
Guerrero Maria
Saile George O.
Taiwan Semiconductor Manufacturing Company
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