Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2001-12-21
2004-08-24
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S696000, C438S697000, C438S699000, C438S700000, C438S705000
Reexamination Certificate
active
06780774
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method of semiconductor device isolation, and more particularly to a method of semiconductor device isolation, which can form a device isolation film on an isolation region of a substrate using a Shallow Trench Isolation (STI) process.
2. Description of the Prior Art
Semiconductor devices formed on a silicon wafer includes a device isolation region serving to electrically isolate circuit patterns from each other. The formation of the device isolation region is an initial process in all fabrication processes, and has an influence upon a size of active regions and a process margin in the subsequent processes. Thus, as the semiconductor devices are highly integrated and fines down, there are actively conducted studies to reduce a size of the respective devices and also to reduce the device isolation region.
Generally, the LOCOS device isolation method widely used in fabrication of semiconductor devices is advantageous in that a process is simple. In a highly integrated semiconductor device of the 256 M DRAM level or above, however, the LOCOS method has limitations due to punch-through by the bird's beak resulted from a reduction in width of the device isolation region, as well as a reduction in thickness of a device isolation film.
For this reason, device isolation methods using a trench, such as the Shallow Trench Isolation (STI), were proposed as technologies suitable for device isolation in the highly integrated semiconductor devices.
FIGS. 1
a
to
1
d
show a method of semiconductor device isolation according to the prior art.
As shown in
FIG. 1
a
, a pad oxide film
102
serving as a buffer film and a silicon nitride film
104
serving to inhibit oxidation are successively formed all over the surface of a semiconductor substrate
100
where a device region II and an isolation region I were defined.
Thereafter, a photoresist film is applied on the silicon nitride film
104
, and then exposed to light and developed, thereby forming a photoresist pattern (PR)
108
through which the isolation region I is exposed.
Next, as shown in
FIG. 1
b
, the silicon oxide film, the pad oxide film and the substrate are etched to a selected depth to form a shallow trench
110
. Then, the photoresist pattern is removed.
After this, in order to recover from surface defects (not shown) caused upon the etching for formation of the trench, the substrate
100
where the trench
110
was formed is subjected to a thermal oxidation process to form a thermal oxide film (not shown) on the substrate. The thermal oxide film is then removed.
Subsequently, as shown in
FIG. 1
c
, on the resulting substrate is formed a gap-fill oxide film
120
filled in the trench
110
. As shown in
FIG. 1
d
, the gap-fill oxide film is etched and planarized using a Chemical Mechanical Polishing (CMP) process in such a manner that the silicon nitride film is exposed.
At the same time, an adhesive oxide film (not shown) may also be interposed between the silicon nitride film
104
and the gap-fill oxide film
120
such that an adhesive strength between the silicon nitride film
104
and the gap-fill oxide film can be increased. The gap-fill oxide film remaining within the trench
120
becomes a device isolation film
121
.
Then, the remaining silicon oxide film and pad oxide film are removed in sequence. Thereafter, a polycrystalline silicon layer
130
for formation of a gate is formed on the resulting substrate.
FIGS. 2
,
3
and
4
are cross-sectional and plane views that show drawbacks occurring in the prior art.
In the method according to the prior art, through forming and removing steps of the thermal oxide film carried out for the purpose of recovering the surface of the substrate having the trench from the defects, a width of the trench is widen so as to reduce a device region, as shown in FIG.
2
. Also, in the subsequent gap-fill oxide deposition and CMP processes and further cleaning process, the upper edge of the trench is recessed as shown by a in
FIG. 3
, and the recessed portion a has a high etching rate.
In addition, in the deposition and patterning processes of the polycrystalline silicon layer for formation of the gate, the polycrystalline silicon remains on the recessed portion a. For this reason, as shown in
FIG. 4
, shorts
1
are caused between word lines
130
on a device region
140
.
SUMMARY OF THE INVENTION
Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a method of semiconductor device isolation, which can easily recover the substrate from the surface defects caused upon the substrate etching process for formation of the trench, while being able to prevent the upper edge portion of the trench from being recessed.
To accomplish this object, there is provided a method of semiconductor device isolation, comprising the steps of providing a semiconductor substrate where a device isolation region was defined; forming a mask on the substrate in such a manner that the device isolation region is exposed through the mask; etching the substrate using the mask to form a trench; thermally treating an inner wall of the trench using the mask under a hydrogen atmosphere; forming a first insulating layer covering the inner wall of the trench; forming a second insulating layer on the mask in such a manner that the second insulating film covers the first insulating film; firstly etching the second insulating layer to expose a surface of the mask; removing the mask; secondly etching the remaining second insulating layer until a surface of the substrate is exposed, thereby forming a device isolation film.
Also, in another embodiment, there is provided a method of semiconductor device isolation, which comprises the steps of providing a semiconductor substrate where a device isolation region was defined; successively forming a buffer oxide film and a silicon nitride film on the substrate; forming a photoresist pattern on the silicon nitride film in such a manner that the device isolation region is exposed through the photoresist pattern; etching the silicon nitride film, the pad oxide film and the substrate using the photoresist pattern as a mask to form a trench; removing the photoresist pattern; thermally treating an inner wall of the trench under a hydrogen atmosphere using the remaining silicon nitride film as a mask; forming an epi-layer covering the resulting inner wall of the trench; forming an insulating layer on the remaining silicon nitride film in such a manner that the insulating layer covers the epi-layer; firstly etching the insulating layer to expose a surface of the remaining silicon nitride film; removing the remaining silicon nitride film; secondly etching the remaining insulating layer until a surface of the substrate is exposed, thereby forming a device isolation film.
REFERENCES:
patent: 5721673 (1998-02-01), Klein
patent: 5960299 (1999-09-01), Yew et al.
patent: 5994756 (1999-11-01), Umezawa et al.
patent: 6093614 (2000-07-01), Gruening et al.
patent: 6306723 (2001-10-01), Chen et al.
patent: 6350662 (2002-02-01), Thei et al.
patent: 04-014829 (1992-01-01), None
patent: 04-134844 (1992-05-01), None
patent: 06-001190 (1994-01-01), None
patent: 09-036323 (1997-02-01), None
patent: 10-144780 (1998-05-01), None
Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
Norton Nadine G.
Tran Binh X
LandOfFree
Method of semiconductor device isolation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of semiconductor device isolation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of semiconductor device isolation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3357313