Electrical computers and digital data processing systems: input/ – Access arbitrating – Access prioritizing
Reexamination Certificate
2002-04-10
2004-11-16
Myers, Paul R. (Department: 2112)
Electrical computers and digital data processing systems: input/
Access arbitrating
Access prioritizing
Reexamination Certificate
active
06820152
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a memory control device for controlling memory access, and especially to a memory control device installed in an LSI (Large Scale Integrated Circuit) for controlling access from a plurality of circuits within the LSI to an external memory connected to the LSI.
(2) Description of the Related Art
In recent years, multimedia information has become increasing common. Against this background along with other factors, developments of LSIs including one or more DSPs (Digital Signal Processors) and MPUs (Micro processing Units) have been proceeding.
Further, developments of complex, high-performance LSIs that include, along with MPUs, independent circuits such as AV (Audio Visual) decoders and hard disk controllers have been proceeding.
Circuits included inside such complex LSIs are independent circuits capable of performing arithmetic operations and other operations to carry out their respective functions using independent local memories. Here, by constructing an LSI such that those circuits share the same memory to perform arithmetic operations and other operations to carry out their respective functions, reduction of the component costs and other effects are realized.
To meet this end, it is required that a memory control device be provided inside an LSI in order to arbitrate contention for access to the shared memory among the circuits.
Memory control devices arbitrate access requests from a plurality of circuits such as DSPs and MPUs (hereinafter referred to as “bus masters”), i.e., bus requests for the usage of a memory bus, so as to permit only one bus master at a time to access the shared memory. That is to say, the memory control device grants a right for the usage of the memory bus to only one bus master at a time.
On the other hand, each bus master issues a bus request to the memory control device when wanting to access the memory, and performs data transfer to or from the memory using the memory bus upon being granted the bus use right.
When there is data to be processed continually in order to, for example, replay image and/or sound in real time, some bus masters are required to transfer the data at a fixed transfer rate.
Such a bus master that is required to transfer data at a fixed transfer rate has an inherent request for time intervals within which the transfer rate is to be maintained. The time intervals are determined depending on the size of input-output buffer included, the type of data processing employed, and other factors. For example, some bus masters are required that the transfer rate of 500 kilo-bytes per millisecond (KB/ms) be maintained with respect to every 2 milliseconds (ms). Some other bus masters are required that the transfer rate of 500 KB/ms be maintained with respect to every 1 ms, which allows a shorter time margin for ensuring the transfer rate.
Provided that the memory is exclusively used, a bus master basically issues a bus request repeatedly at the time intervals within which the transfer rate should be maintained. Hereinafter, such time intervals within which the transfer rate should be maintained are referred to as bus request cycles.
In order to design an LSI which includes: a plurality of bus masters requiring data transfer at a fixed transfer rate; and a memory control device, it is necessary to construct an arbiter mechanism in the memory control device in consideration of a transfer rate and a bus request cycle that are required for each bus master.
Under appropriate arbitration, each bus master is allowed to transfer data at a requested transfer rate. However, in the case where arbitration is inappropriate, there may be a problem that one or more of the bus masters fail to transfer data at their requested transfer rates within their bus request cycles.
Conventional memory control devices typically include an arbiter mechanism employing a priority scheme in which priority is given on a first-come first-served basis, or a priority scheme in which each bus master is arbitrated in accordance with their assigned priorities.
Hereinafter, description is given to problems associated with such conventional memory control devices.
Here, consideration is given to the case where the bandwidth of a memory bus is about 800 KB/ms and an LSI includes two bus masters A and B. When there is data to be processed continually, the bus A is required to transfer 1000 KB of data within a bus request cycle of 2 ms, while the bus master B is required to transfer 100 KB of data within a bus request cycle of 1 ms, which allows only half the time margin comparing to the bus request cycle of the bus master A. Further, it is assumed that a first-come first-served basis priority scheme is employed and that the bus master A issues a bus request first. Alternatively, it is assumed that arbitration is carried out based on their priorities and that the bus master A has a higher priority.
In both cases, when the bus master A issues a bus request to a conventional memory control device, the memory control device grants a bus use right to the bus master A to permit data transfer. In response, the bus master A transfers 1000 KB of data, which takes 1 ms or longer. As a result, the memory control device is unable to immediately respond to a bus request from the bus master B which is issued every 1 ms.
Under the circumstances, the bus master B has to put up with the latency time longer than 1 ms to access memory. Consequently, the bus master B fails to uniformly transfer 100 KB of data to or from the memory in each cycle of 1 ms, which results in inconsistent data transfer. In other words, the transfer rate required for the bus master B is not maintained within each bus request cycle.
As described above, the conventional memory control device having an arbitrating mechanism based on a first-come first-served basis or an assigned priority basis may manage to ensure the transfer rate required for each bus master on a long-term basis. However, such a conventional memory control device is incapable of ensuring the transfer rates on a short-term basis, which is a problem.
To address the above problem, a memory control device needs to be designed with consideration given in advance to the transfer rate required for each bus maser and the time intervals within which the transfer rate needs to be ensured.
However, a process that each bus master is required to perform differs depending on a device into which an LSI is incorporated. Consequently, the transfer rate and bus request cycle required for each bus master differ. Under these circumstances, it is extremely difficult to design a memory control device with consideration given in advance to specific processes that each bus master is later required to perform.
Further, LSIs have been improved year after year. In view of cost reduction incurred for future development of incorporating a new circuit into LSIs, there is a demand for developing and designing a versatile memory control device capable of ensuring data transfer rates of whatever circuits incorporated into the LSI. Such a versatile memory control device will realizes the use of the designing resources over a long period of time.
SUMMARY OF THE INVENTION
The present invention is made in view of such demand as above, and aims to provide a versatile memory control device that arbitrates contention for memory access while ensuring the transfer rate required for each bus master within the time periods required for each bus master. The present invention also aims to provide an LSI including such a memory control device and bus masters.
To achieve the above objects, a memory control device of the present invention is for arbitrating memory access contention among a plurality of bus masters sharing a memory by selectively granting a bus use right that permits the usage of a memory bus to one of the plurality of bus masters at a time, and the memory control device comprises: holding means for holding transfer rate information regarding each of the plurality of the bus masters, the transfer rate
Kanzaki Hideyuki
Osaka Masataka
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