Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output access regulation
Reexamination Certificate
2001-03-29
2004-06-01
Perveen, Rehana (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output access regulation
C710S107000, C711S118000, C714S047300
Reexamination Certificate
active
06745261
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an external storage subsystem, and more particularly to a technology effective for an improvement of reliability of an external storage subsystem having a cache function.
For example, in a magnetic disk subsystem used as an external storage in a general purpose computer system, a well-known cache memory comprising a semiconductor memory is interleaved at a portion of a disk controller to avoid as much as possible the reduction of a data transfer rate due to a mechanical factor such as a rotational delay time or a latency time in a magnetic disk drive.
A cache structure in such a disk controller is discussed in “A Multiport Page-Memory Architecture and A Multiport Disk-Cache System” New Generation Computing 2 (1984) 241-260 OHMSHA, LTD. and Springer-Verlag, in which it is proposed to improve an access performance to the cache by dividing into a plurality of memory banks. Further, a switching network called an interconnection network is proposed as a system for coupling the memory banks and a channel or a disk controller.
The conventional technology above intends to improve the cache performance by providing a plurality of memory banks and the switching network. As to a data bus structure in the disk controller, the switching network system called the interconnection network is proposed. However, the switching network system is imparted with a hardware restriction when a data bus configuration for exchanging data is to be constructed by connecting a plurality of memory banks and a plurality of channel units or a plurality of control units.
It does not refer to the multiplexity of the cache unit comprising the memory banks.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a data bus structure for connecting a plurality of cache units of a host and a plurality of channel units or a plurality of control units of a rotating storage, by taking restrictive conditions of a data transfer rate and a data bus width on hardware into consideration.
It is another object of the present invention to provide an external memory subsystem which has a high tolerance to failures and has a highly reliable cache function.
The above and other objects and features of the present invention will be apparent from the following description of the present invention when taken in conjunction with the attached drawings.
Representative features of the present invention are briefly explained below.
The external storage subsystem of the present invention comprises a rotating storage for storing data to be accessed from a host and an external memory control unit having a cache mechanism for responding to an access request from the host to the rotating storage by temporarily holding data exchanged between the rotating storage and the host and having at least one of a non-volatile (persistent) semiconductor memory and a volatile (non-persistent) semiconductor memory as a storage medium. It further comprises a plurality of independent cache mechanisms and a plurality of independent access paths for permitting independent accesses from the host and the rotating storage to the respective cache mechanisms.
In the external storage subsystem of the present invention, the external memory control unit comprises a plurality of channel units for controlling the transfer of data to and from the host and a plurality of control units for controlling the transfer of data to and from the rotating storage, and each of the channel units and the control units has a plurality of the first access paths to which a plurality of cache mechanisms are to be independently connected.
In the external storage subsystem of the present invention, the external memory control unit comprises a plurality of channel units for controlling the transfer of data to and from the host and a plurality of control Units for controlling the transfer of data to and from the rotating storage, and each of the cache mechanisms has a plurality of the second access paths to which the channel units and the control units are to be connected.
In the external storage subsystem of the present invention, the external memory control unit comprises a plurality of channel units for controlling the transfer of data to and from the host, a plurality of control units for controlling the transfer of data to and from the rotating storage, and a plurality of independent access paths to the channel units, the control units and the cache mechanisms. The respective channel units, control units and cache mechanisms are connected to the third access paths.
In the external storage subsystem of the present invention, the external memory control unit comprises a plurality of channel units for controlling the transfer of data to and from the host, a plurality of control units for controlling the transfer of data to and from the rotating storage, and the fourth access paths for directly and independently connecting the respective channel units and control units with the respective cache mechanisms.
In the external storage subsystem of the present invention, since the cache units are multiplexed and the access paths to the respective cache units by the host and the rotating storage are of independent configuration, the data transfer rate or the data bus width can be optimized by combining a plurality of cache units and a plurality of channel units or a plurality of control units.
Further, since the cache units and the access paths to the cache units are multiplexed, a probability of maintaining the cache function in case a trouble occurs is enhanced and the reliability of the external storage subsystem and the tolerance to the failures are certainly improved.
The effects of the representative features of the present invention are as follows.
In the external storage subsystem of the present invention, the cache units in the external storage subsystem including the rotating storage can be coupled, in a simple construction, to the channel units of the host and the control units of the rotating storage. Accordingly, the cache function and performance in the disk control unit are improved.
Further, in the external storage subsystem of the present invention, since both the cache units and the access paths to the cache units are multiplexed, the tolerance to the failures is high and the highly reliable cache function is attained.
REFERENCES:
patent: 4021784 (1977-05-01), Kimlinger
patent: 4394732 (1983-07-01), Swenson
patent: 4467414 (1984-08-01), Akagi et al.
patent: 4722084 (1988-01-01), Morton
patent: 4723223 (1988-02-01), Hanada
patent: 4792898 (1988-12-01), McCarthy et al.
patent: 4920478 (1990-04-01), Faruya et al.
patent: 4996641 (1991-02-01), Talgam et al.
patent: 5019971 (1991-05-01), Lefski et al.
patent: 5073851 (1991-12-01), Masterson et al.
patent: 5123099 (1992-06-01), Shibata et al.
patent: 5124987 (1992-06-01), Milligan et al.
patent: 5133060 (1992-07-01), Weber et al.
patent: 5142627 (1992-08-01), Elliot et al.
patent: 5150465 (1992-09-01), Bush et al.
patent: 5155845 (1992-10-01), Beal et al.
patent: 5175842 (1992-12-01), Totani
patent: 5204836 (1993-04-01), Reed
patent: 5210843 (1993-05-01), Ayers
patent: 5228135 (1993-07-01), Ikumi
patent: 5253351 (1993-10-01), Yamamoto et al.
patent: 5257359 (1993-10-01), Blasco et al.
patent: 5269019 (1993-12-01), Peterson et al.
patent: 5274790 (1993-12-01), Suzuki
patent: 5287480 (1994-02-01), Wahr
patent: 5289478 (1994-02-01), Barlow et al.
patent: 5325488 (1994-06-01), Carteau
patent: 5459856 (1995-10-01), Inoue
patent: 5465343 (1995-11-01), Henson et al.
patent: 5519831 (1996-05-01), Holzhammer
patent: 5555391 (1996-09-01), De Subijana et al.
patent: 5689729 (1997-11-01), Inoue
patent: 6295577 (2001-09-01), Anderson et al.
patent: 445479 (1995-07-01), None
patent: 035899 (1926-02-01), None
patent: 63-225848 (1988-09-01), None
A Multiport Page-Memory Architecture and a Multiport Disk-Cache Sysem, New Generation Computing 2 (1984) 241-260, Ohmsha, Ltd. and Springer-Verlag.
Hitachi , Ltd.
Mai Rijue
Perveen Rehana
LandOfFree
Method for connecting caches in external storage subsystem does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for connecting caches in external storage subsystem, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for connecting caches in external storage subsystem will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3356114