Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-07-18
2004-08-24
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S233000
Reexamination Certificate
active
06781171
ABSTRACT:
TECHNICAL FIELD
The present disclosure pertains to a pinned photodiode and, more particularly, a pinned photodiode for a CMOS image sensor having enhanced performance and a method of making the pinned photodiode.
BACKGROUND
In a conventional complimentary metal oxide semiconductor (CMOS) image sensor, a pinned photodiode using three transistors attracts excess electrons generated by incident light on a photodiode area and uses a drive transistor to transfer the excess electrons. In such conventional art, a potential well where electrons are attracted and stored is formed on one corner of photodiode area around a contact. Therefore, electrons generated by light can recombine while moving to a potential well because of the long distance between a location where the electrons are generated and the location of the potential well where the electrons are drawn by a drive transistor. This results in poor transistor operation characteristics. In addition, the photodiode area accepting light rays is decreased in size because the area of the potential well formed is excessively broad, thereby having negative influences on device operation characteristics.
Such problems in the prior art are described referring to
FIGS. 1 and 2
.
FIG. 1
is a layout of a conventional photodiode having three transistors, illustrating the trajectory of excess electrons generated by light are transferred. As shown in
FIG. 1
, a layout of a conventional photodiode having three transistors includes a photodiode area
1
, a supply voltage line
5
, a select transistor
2
, a drive transistor
3
, a reset transistor
6
, an N+ potential well area
7
b
, and a contact
4
.
FIG. 2
is a cross-sectional view of
FIG. 1
taken along lines A-A′, illustrating a cross-section of a known pinned photodiode. A conventional photodiode has a first N+ potential well area
7
a
as an N type impurity area, which is formed between a P type substrate
8
and the photodiode area
1
, and a second N+ potential well
7
b
that is positioned more deeply than the first N+ potential well
7
a
and formed on a part of the P type substrate
8
where the photodiode area
1
is not formed, near a reset transistor
6
. As shown
FIG. 2
, excess electrons generated by light in a pinned photodiode are transferred into the deeply formed second N+ potential well
7
b.
Thus, in a conventional pinned photodiode, excess electrons are generated on a photodiode area when a pixel area accepts light rays, and the excess electrons are stored in another potential well. A pinned photodiode with three transistors has another deeper potential well, which is located right next to a reset transistor, than a potential well on a photodiode area. Therefore, excess electrons generated are stored in the deeper potential well due to a characteristic of electrons that prefer stable state, and, subsequently, are transferred through a contact.
However, because the deeper potential well is located next to a reset transistor positioned on one corner of a pinned photodiode, excess electrons generated by light on a pinned photodiode area can be recombined during movement to the deeper potential well. In addition, such disadvantage has a negative effect on transistor operation characteristics by reducing photocurrent of a photodiode.
REFERENCES:
patent: 5625210 (1997-04-01), Lee et al.
patent: 5903021 (1999-05-01), Lee et al.
patent: 6027955 (2000-02-01), Lee et al.
Jang Hoon
Lim Keun Hyuk
Dongbu Electronics Co. Ltd.
Grossman & Flight LLC
Pham Long
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