Heterointegration of materials using deposition and bonding

Details Heterointegration of materials using deposition and bonding Heterointegration of materials using deposition and bonding

2001-01-17

2004-06-15

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S602000, C438S933000

Reexamination Certificate

active

06750130

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to the field of heterointegration of materials using deposition and bonding.
The goal of combining different materials on a common substrate is desirable for a variety of integrated systems. Specifically, it has been a long-standing desire to combine different semiconductor and oxide materials on a common useful substrate such as a silicon substrate. However, just as the different materials properties are beneficial from the system application perspective, other properties make such materials combinations problematic in processing.
For example, semiconductor materials with different properties often have different lattice constants. Therefore, deposition of one semiconductor material on top of another substrate material results in many defects in the semiconductor layer, rendering it useless for practical application. Another method of integrating materials is through the use of wafer bonding. The bonding process removes the lattice mismatch problem. However, this problem is replaced with a mismatch in thermal expansion. Due to the different thermal expansion coefficients in the bonded materials, the materials cannot be subsequently processed or annealed at optimum temperatures without inducing material degradation (i.e. greater residual stress or introduction of dislocations). A final issue is that due to the different material properties, the bulk crystal materials are often different size (boule diameter). This disparity is undesirable for wafer bonding since only a portion of the composite is useful for device/system fabrication.
SUMMARY OF THE INVENTION
Accordingly, the invention provides a semiconductor structure including a first substrate, and an epitaxial layer bonded to the substrate. The epitaxial layer has a threading dislocation density of less than 10
7
cm
−2
and an in-plane lattice constant that is different from that of the first substrate and a second substrate on which the epitaxial layer is fabricated. In an exemplary embodiment, the epitaxial layer is a segment of a previously fabricated layered structure including the second substrate with a compositionally graded layer and the epitaxial layer provided thereon. The second substrate and the graded layer are removed subsequent to the layered structure being bonded to the first substrate.
In accordance with another exemplary embodiment of the invention, there is provided a method of processing a semiconductor structure including providing a first substrate; providing a layered structure including a second substrate having an epitaxial layer provided thereon, the epitaxial layer having an in-plane lattice constant that is different from that of the first substrate and a threading dislocation density of less than 10
7
cm
−2
; bonding the first substrate to the layered structure; and removing the second substrate.


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