Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-05-16
2004-02-10
Le, Dung A (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S672000, C438S673000, C438S674000, C438S675000, C438S700000
Reexamination Certificate
active
06689683
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method of manufacturing a semiconductor device and particularly, but not limited to, a method of forming a barrier metal and a metal buried in a depression formed in a substrate. The present application is based on Japanese Patent Application No. 2001-148585, which is incorporated herein by reference.
2. Description of the Related Art
Conventional semiconductor integrated circuits have been using, as a material for metal wiring, aluminum or an aluminum-based metal composed of an aluminum alloy because these materials exhibit lower specific resistance and permit easier patterning. Recently, however, a Cu or Cu-based metal composed of a Cu alloy is being used that exhibits lower resistivity and higher electromigration (EM) resistance than those of aluminum-based metals. This trend is based on the recent increasing demand for higher integration, more compactness, higher speed, and higher reliability in semiconductor integrated circuit, such as LSIs.
To make wires by using such a Cu-based metal, it is difficult to form a desired wire because the Cu-based metal does not permit easy dry etching. A method has been disclosed in Japanese Patent Application Laid-Open No. 2000-183160, wherein a concave (trench) of a wiring pattern is formed in an interlayer dielectric, a Cu film is deposited on the entire surface, the trench is embedded, and chemical mechanical polishing (CMP) is carried out to remove the Cu film exposed on the interlayer dielectric so as to form an embedded wiring with the Cu film left in the trench. This technique is known as a damascene process. The damascene process may be divided into a single damascene process whereby only wiring is formed and a dual damascene process whereby contact holes or via holes for the connection with the wiring of a lower layer are also formed in addition to wiring. The dual damascene structure permits the number of steps to be reduced, thus contributing to reduced cost. As the method for filling a wire or the recessed portion between a wire and a via hole with a Cu film, the high-temperature reflow method, the sputtering method, and the electrolytic plating method are known, among which the electrolytic plating method is ideally used for filling a recessed portion exhibiting a high aspect ratio.
FIGS. 1A through 1E
illustrate the dual damascene process. Referring to
FIG. 1A
, a first metal wire
103
having a barrier metal layer
102
and an interlayer dielectric
104
covering the first metal wire
103
are formed on a semiconductor substrate
101
on which elements have been formed. Then, a wiring trench
105
and a via hole
106
connected to the first metal wire
103
through the trench
105
are opened in the surface of the interlayer dielectric
104
by lithography and dry etching. Subsequently, as shown in FIG.
1
B and
FIG. 1C
, a barrier metal layer
107
made of Ta or the like and a seed layer
108
made of Cu or the like are formed in sequence onto the inner surfaces of the trench
105
and the via hole
106
by a barrier metal/seed layer forming apparatus. The barrier metal layer and the seed layer are processed in the same vacuum atmosphere. Thereafter, as shown in
FIG. 1D
, the recessed portion of the via hole
106
and the trench
105
is filled with a plating metal
109
by plating method or the like wherein the seed layer
108
provides a plating electrode. The plating metal
109
is formed integrally with the seed layer
108
. Next, as shown in
FIG. 1E
, the plating metal
109
, the seed layer
108
, and the barrier metal layer
107
that expose on the interlayer dielectric
104
are polished to be removed by the CMP method so as to form a second wire
110
and a contact hole
111
filled with the metal. Repeating the above procedure forms multilayer wiring.
To fill the recessed portion of the trench and via hole or the like with a metal film formed of Cu or the like by the electrolytic plating method, it is necessary to form a seed Cu layer providing a cathode in the plating process on the side surfaces and the bottom surface of the recessed portion in advance. By using the sputtering method, the barrier metal layer, which provides a Cu barrier layer, and the seed Cu layer are formed on the interlayer dielectric including the recessed portion, then plating is carried out to fill the recessed portion with Cu, using the seed layer as the cathode.
There has been accelerating demand for smaller wiring widths with the increasing microminiaturization of semiconductor integrated circuits. With this trend, the aspect ratios of trench and via holes are increasing. Via holes having an aspect ratio exceeding 4, for example, require filling by Cu. However, in the case of the trench and via hole or the like having high aspect ratios, as shown in the photograph of FIG.
8
and
FIG. 11
showing the schematic diagrams of the photograph of
FIG. 8
, when an attempt is made to form the seed Cu layer
108
by sputtering on the bottom surface and side surfaces thereof after forming the barrier metal layer
107
on the inner surface of the recessed portion
106
, there are some cases where adequate coverage is not accomplished.
Especially on the side surfaces near the bottom of the recessed portion
106
, the seed Cu layer
108
is attached in a minute island state rather than being a continuous layer. For this reason, in this area, Cu hardly or insufficiently grows from the seed Cu layer
108
even when the plating is carried out. This happens because a Cu electrolytic plating bath (CuSO
4
.5H
2
O+H
2
SO
4
) exhibits strong acidity, so that the island-like seed Cu layer is melted away by the electrolytic plating bath faster than the growth of the Cu layer by the plating. Thus, the Cu is grown by the plating in the upper area of the recessed portion
106
, that is, the area where the seed Cu layer
108
has been continuously formed, while Cu hardly or insufficiently grows in the lower area of the recessed portion
106
, that is, the area where the seed Cu layer
108
has been formed in the island state. As a result, the recessed portion
106
cannot be completely filled with Cu, leading to the formation of voids.
To improve the poor formation the seed layer on the lower area of the recessed portion, it can be considered to increase the thickness of the seed layer by, for example, extending the sputtering time. In this case, however, the seed layer would be thick at the opening of the recessed portion, causing the seed layer to considerably overhang. As a result, the Cu that has grown at the opening before the filling of the recessed portion is completed may close or pinch off the opening, causing a large void to be formed in the recessed portion. Therefore, the thickness of the seed layer cannot be increased much.
As a solution to the above problem, Japanese Unexamined Patent Publication No. 2000-183160 has disclosed a method in which the seed layer formed by electroless plating is reinforced to prevent the seed layer from being formed in an island state, then electrolytic plating is carried out to charge Cu. According to this method, however, a plating apparatus is required to be additionally equipped with a plating bath for performing the electroless plating, posing a problem of a more complicated apparatus. This is another problem in that the electroless plating is generally poor in the aspect of stability and reproducibility, leading to poor mass productivity.
To improve the coverage of a seed layer, it is conceivable to use a long slow sputtering method in which the distance between a substrate and a target is set to be longer than usual or an ionized sputtering method in which Cu is ionized and Cu ions are positively drawn into a recessed portion by applying a substrate bias. However, even if these methods are used, because the side walls of the recessed portion have a relatively thinner seed Cu layer, the temperature of the substrate increases due to the bombardment of sputtered atoms, ions, etc. during a sputtering process,
Le Dung A
McGinn & Gibb PLLC
NEC Electronics Corporation
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