Memory architecture for TCCT-based memory cells

Static information storage and retrieval – Systems using particular element – Semiconductive

Reexamination Certificate

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C365S148000, C365S149000

Reexamination Certificate

active

06778435

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuits, and in particular, to a memory architecture for facilitating storage and access of data in memory cells, such as in thinly capacitively-coupled thyristor (“TCCT”) based memory cells.
2. Description of Related Art
Random Access Memories (“RAM”) are memories capable of multiple read-write cycles and are widely used to temporally store data in computing applications. A typical RAM is structured to include numerous memory cells arranged in an array of rows and columns wherein each memory cell is designed to store a datum or unit of data as a binary digit (i.e., a binary zero or a binary one). Each row of the memory cell array is typically connected to a word line and each column of the memory cell array is typically connected to a bit line (or a pair of complementary bit lines in an SRAM-based memory). The typical RAM structure also includes other circuitry to effect traditional read and write operations, such as reference signal generation circuitry, signal sensing circuitry, and control signal circuitry.
Reference signal generation circuitry is designed to provide a reference in which to compare a data signal (e.g., voltage or current) representing the unit of data stored in a memory cell. Depending on the memory cell, the reference signal can be a complementary signal, such as in an SRAM device, or an independently derived reference signal, such as in a DRAM device. Independently derived reference signals are generated by memory cells known as reference cells, where reference cells are well known for providing a reliable and accurate reference signal (e.g., reference voltage or current) in which to compare the data signal.
The term “device” herein is used to describe both a discrete semiconductor circuit element, such as a MOS transistor or a TCCT device, as well as a semiconductor product. A memory semiconductor product can be referred as a memory “chip” or “integrated circuit (“IC”)” and is a circuit element operating cooperatively with other semiconductor products, such as a microprocessor.
Signal sensing circuitry is employed to sense whether the value of the voltage or current representing the unit of data is a logical one or zero. A typical signal sensing circuit is a sense amplifier operating as a differential amplifier. Sense amplifiers (“sense amps” or “SAs”) are designed to receive the reference signal and the data signal, and thereafter, resolve the data signal into a logical one or zero. Control signal circuitry includes read and write signals to effect such functions and more specifically includes memory address decoding signals, and other signals such as a write driver select control signal.
Not only do RAM memory cells, reference cells and/or sense amplifiers each influence memory architecture design, but three primary design considerations also govern the design thereof. These primary considerations are circuit space, power consumption, and speed, each of which are traditionally traded-off or emphasized at the expense of the others. Such considerations are predominantly governed by the structure and layout of the constituent memory cells, such as SRAM, DRAM and T-RAM cells.
FIGS. 1A and 1B
schematically show an SRAM-based memory cell and a DRAM-based memory cell, respectively.
FIG. 1A
is a general schematic of a typical SRAM memory cell composed of metal oxide semiconductor (“MOS”) devices A, B in a cross-coupled arrangement with a pair of bit lines (“BL”). Devices A are pass transistors designed to operate when an appropriate word line (“WL”) signal is applied to the transistor gates. In particular, devices A operate as switches to provide stored data from each cell to one of complementary pair of bit lines BL and BL
bar
. Devices L are resistors or pull-up transistors to provide appropriate loads to offset charge leakage from the storage transistors represented as devices B. Devices B of
FIG. 1A
arc storage devices designed to store information as a binary data bit. In a read operation, the word line activates devices A and the SRAM cell provides a stored voltage from a drain of each device B to its respective bit line.
Conventional SRAM chips often employ memory architectures that emphasize two of these primary design considerations at the expense of a third. For example,
FIG. 1A
is a schematic representation of a conventional SRAM based on a six-transistor (“6T”) cell (i.e., two transistors and two resistors plus two cell-access transistors). In another conventional SRAM cell, referred to as a four-transistor (“4T”) SRAM cell (not shown), the cell includes four cross-coupled transistors. Such cells are compatible with mainstream CMOS technology, consume relatively low levels of standby power, operate at low voltage levels, and perform at relatively high speeds. Conventional 4T and 6T SRAM cells, however, use a large cell area and thus significantly limit the maximum density of such SRAM cells in an array. Consequently, traditional SRAM memory architectures typically are designed to leverage their high speed and low power characteristics at the cost of additional layout area.
FIG. 1B
is a general schematic of a typical DRAM memory cell that includes a MOS device C including a gate connected to a single word line (i.e., row) to enable the cell to store a voltage representing a data bit of information on capacitor CAP. Bit line BL (i.e., column) is used to read data from or to write data to the DRAM cell.
Conventional DRAM chips also employ memory architectures that compromise trade-offs between the three primary design considerations discussed above. DRAM devices, in contrast to SRAM devices, are generally fabricated in arrays with higher densities (i.e., memory cells per unit area) of DRAM cells than SRAM arrays because the individual memory cells of a DRAM include fewer transistors than the individual cells of an SRAM. DRAM cells, unlike SRAM cells, must be periodically refreshed to prevent loss of data. To refresh DRAM cells, additional charge is added to bit lines in a DRAM architecture. The additional charge and bit line capacitance, however, causes read and write operations with DRAM cells to execute at lower speeds than in SRAM memory architectures. Consequently, DRAM memory architectures are designed to provide high cell densities at the expense of speed.
FIG. 1C
is a TCCT memory cell as described in U.S. Pat. No. 6,229,161, which is issued to Nemati et al. (“the Nemati patent”) and incorporated herein by reference in its entirety for all purposes. A TCCT based memory cell, alternatively referred to as a T-RAM cell (i.e., Thyristor-RAM), has an “on” state wherein it generates a current to represent a logic “1” that is received by the bit line, and has an “off” state wherein it produces essentially no current to represent a logic “0.” The TCCT memory cell generally is adapted to operate with two unique word lines—a first word line referred to as word line one (“WL
1
”) and a second word line referred to as word line two (“WL
2
”), both of which include at least one line end referred to herein as a terminus. WL
1
is coupled to the gate of access device S, where access device S provides access to storage cell T for transferring bit information between the TCCT memory cell T and the bit line during both read and write operations. WL
2
is coupled to TCCT memory cell T and is typically activated only for writing data to the device.
In a proper cell write operation, however, both WL
1
and WL
2
are activated to transfer a data signal from the bit line to TCCT memory cell T for data storage. To write a logical “0” into TCCT cell T, a bit line voltage is raised to a relatively high potential, such as V
dd
. Conversely, to write a logical “1,” into TCCT cell T, a voltage having a relatively low potential (i.e., 0v or ground) is applied to the bit line. In both cases, WL
2
is activated to accomplish writing both logical “0” and “1” into the TCCT memory cell T for storage.
It should be noted that if WL
2
is enabled without WL
1
enab

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