Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
2002-05-06
2004-08-03
Perveen, Rehana (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C710S060000, C709S241000, C709S241000, C709S241000, C712S225000
Reexamination Certificate
active
06772244
ABSTRACT:
TECHNICAL FIELD AND BACKGROUND ART
This invention relates to methods and devices for dealing with slow processing times in systems with input queues.
Input queues are used to buffer transactions that one or more transaction processors cannot immediately service. The initiator of the transaction may expect a response from the processor within a maximum amount of time called a timeout period. If the processing rate of the processor(s) is at times too slow to keep up with the flow of transactions, a response to a transaction may be sent to the initiator after the timeout period. After the timeout period, the initiator may no longer expect a response from the transaction request and receipt of a response may cause the system to crash. Even when the initiator has prepared for the possibility of such delayed responses, these delayed responses can lead to degraded system performance.
SUMMARY OF THE INVENTION
In an embodiment of the invention, a method for reducing the incidence of stale transactions in a queuing system is provided. Deviations from a maximum expected processing time (“MEPT”) for processing a transaction are summed and compared to a threshold time. When the sum of deviations exceeds the threshold time, a response such as discarding transaction request in an input queue is initiated.
In a further embodiment of the invention, additional steps are taken to ensure that transactions that arrive in an input queue after the system has been idle for a period of time are not discarded. Such steps may include allowing the sum of time deviations of to decay as a function of time when the input queues are empty. Alternatively, the sum of deviations may decay when the input queues are empty and the transaction processors are idle. Further, the count of incoming transactions to be discarded may be set to zero when the count of transactions to be discarded has not incremented for a predetermined time period.
Embodiments of this invention advantageously eliminate or reduce the frequency with which transaction processing request responses are sent to an initiator of a transaction request after the initiator has timed out the request.
REFERENCES:
patent: 5095369 (1992-03-01), Ortiz et al.
patent: 5471614 (1995-11-01), Kakimoto
patent: 5628013 (1997-05-01), Anderson et al.
patent: 6477558 (2002-11-01), Irving et al.
“Minimizing Apparent Processor Deadlock”, IBM TDB, Mar. 1991, vol. 33, Issue 10A, pp. 85-86.
Hagersten Erik
Morrier Don M.
Nguyen Hien H.
Wong-Chan Monica
Kivlin B. Noäl
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Perveen Rehana
Sun Microsystems Inc.
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