Method for reducing dimensions between patterns on a...

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

Reexamination Certificate

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C438S696000, C438S703000, C438S714000, C438S725000, C438S947000, C438S951000

Reexamination Certificate

active

06750150

ABSTRACT:

DESCRIPTION OF THE INVENTION
1. Field of the Invention
This invention relates in general to a semiconductor manufacturing process and, more particularly, to a photolithographic method having reduced dimensions between patterns on a photoresist.
2. Background of the Invention
With sub-micron semiconductor manufacturing process being the prevalent technology, the demand for a high-resolution photolithographic process has increased. The resolution of a conventional photolithographic method is primarily dependent upon the wavelength of a light source, which dictates that there be a certain fixed distance between patterns on a photoresist. Distance separating patterns smaller than the wavelength of the light source could not be accurately patterned and defined.
Prior art light sources with lower wavelengths are normally used in a high-resolution photolithographic process. In addition, the depth of focus of a high-resolution photolithographic process is shallower compared to a relative low-resolution photolithographic process. As a result, a photoresist layer having a lower thickness is required for conventional photolithographic methods. However, a photoresist layer having a lower thickness is susceptible to the subsequent etching steps in a semiconductor manufacturing process. This relative ineffective resistance to etching reduces the precision of patterning and defining of a photoresist. These limitations prevent the dimensions of patterns on a photoresist from being reduced.
It is accordingly a primary object of the invention to provide a method for reducing the distance separating patterns on a photoresist layer. In addition, it is another object of the invention to provide a method to enhance the etching resistance of a patterned photoresist layer.
SUMMARY OF THE INVENTION
In accordance with the invention, there is provided a semiconductor manufacturing method that includes depositing a layer of semiconductor material over a substrate, providing a layer of photoresist over the layer of semiconductor material, patterning and defining the photoresist layer, depositing a layer of inorganic material over the patterned and defined photoresist layer, wherein the layer of inorganic material is photo-insensitive, anisotropic etching the layer of inorganic material and the layer of semiconductor material, and removing the patterned and defined photoresist layer.
In another aspect, the layer of inorganic material is substantially conformal.
In yet another aspect, the step of depositing a layer of inorganic material is performed at a temperature lower than a stability temperature of the patterned and defined photoresist layer.
Also in accordance with the present invention, there is provided a semiconductor manufacturing method that includes defining a substrate, depositing a layer of semiconductor material over the substrate, providing a layer of photoresist over the layer of semiconductor material, patterning and defining the photoresist layer to form at least one photoresist structure having at least one substantially vertical sidewall and one substantially horizontal top, depositing a photo-insensitive material over the at least one photoresist structure and the layer of semiconductor material, wherein an amount of the photo-insensitive material deposited on the top of the photoresist structure is substantially greater than an amount of the photo-insensitive material deposited on the at least one sidewall of the photoresist structure, etching the photo-insensitive material and the layer of semiconductor material, and removing the at least one photoresist structure.
In one aspect, the amount of the photo-insensitive material deposited on the top of the photoresist structure is substantially greater than an amount of the photo-insensitive material deposited on the layer of semiconductor material.
Further in accordance with the present invention, there is provided a semiconductor manufacturing method that includes defining a substrate, providing a first layer over the substrate, providing a layer of photoresist over the first layer, patterning and defining the photoresist layer to form at least two photoresist structures, wherein each of the photoresist structures includes substantially vertical sidewalls and a substantially horizontal top, and wherein the photoresist structures are separated by a space, depositing a layer of polymer on the tops of the photoresist structures and the space separating the photoresist structures, wherein an amount of the polymer deposited on the tops of the photoresist structures is substantially greater than an amount of the polymer deposited on the sidewalls of the photoresist structures, and etching the polymer layer on the tops of the photoresist structures and the space between the photoresist structures, and the first layer.
In one aspect, the first layer is a dielectric layer.
Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments of the invention and together with the description, serve to explain the principles of the invention.


REFERENCES:
patent: 4586980 (1986-05-01), Hirai et al.
patent: 4707218 (1987-11-01), Giammarco et al.
patent: 4838991 (1989-06-01), Cote et al.
patent: 4871630 (1989-10-01), Giammarco et al.
patent: 4962054 (1990-10-01), Shikata
patent: 5618383 (1997-04-01), Randall
patent: 5770510 (1998-06-01), Lin et al.
patent: 6100014 (2000-08-01), Lin et al.

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