Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-06-30
2004-11-16
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S640000
Reexamination Certificate
active
06818539
ABSTRACT:
Japanese patent application no. 11-186638, filed Jun. 30, 1999, is hereby incorporated by reference in its entirety. Japanese patent application no. 2000-162322, filed May 31, 2000, is hereby incorporated by reference in its entirety.
FIELD OF THE INVENTION
The present invention relates to a pad structure of a semiconductor device, particularly to semiconductor devices having a pad on which a connection is formed, and methods of fabricating the same.
BACKGROUND
In spite of improvement of high integration of semiconductor integrated circuits and miniaturization of semiconductor chips, it has been difficult to reduce the size of a pad having a region electrically connected with the external components to a satisfactory level. This is because a pad has to be provided with a certain dimension to ensure stable electric connection with bonding wires, bumps, and the like, and to avoid a high resistance in the connecting point.
In addition, for a pad on which a bump is formed, it should be considered to keep adequate coverage for an aperture in a protective insulating layer. If there is a large and steep step around an aperture in a protective insulating layer, a barrier layer may not exhibit adequate coverage, resulting in breakage of the barrier layer.
For example, Japanese Patent Application Laid-open No. 10-189606 discloses a technique to attempt to overcome such a problem. In the technique of this patent application, a protective insulating layer formed on a metal pad of a semiconductor substrate has a connection aperture having steps for a bump of a semiconductor device. In forming such a protective insulating layer, an insulating layer on a metal pad is subjected to photo etching several times using a plurality of masks with different diameters to form an aperture having steps. Since this method requires a number of photolithography steps, a plurality of photo-masks are necessary for the photolithographic operation. As a result, although the coverage of the barrier layer is improved by this method, a cleaning step or the like is required during and prior to each photolithographic operation. This results in an undesirable increase in the number of fabrication steps and production costs.
SUMMARY
One embodiment relates to a semiconductor device including a pad which is formed on an insulating layer. The pad includes an electric connection region to connect with external components. The device includes a protective insulating layer which is formed on the insulating layer and the pad and has an aperture for exposing the electric connection region. At least part of a side surface of the protective insulating layer surrounding the electric connection region is a tapered surface with an acute angle to a top surface of the pad. The protective insulating layer includes at least first and second insulating layers, each of which has a side surface exposed to the aperture.
Another embodiment relates to a semiconductor device including a pad which is formed on an insulating layer and includes an electric connection region to connect with external components. The device includes a protective insulating layer which is formed on the insulating layer and the pad and includes an aperture over at least part of the electric connection region. A side surface of the protective insulating layer surrounding the electric connection region is a tapered surface with an acute angle to a top surface of the pad.
Another embodiment relates to a method of fabricating a semiconductor device including: forming a pad with a predetermined pattern on an insulating layer; forming a protective insulating layer on the insulating layer and over the pad by sequentially forming at least first and second insulating layers; forming a mask layer on the protective insulating layer, the mask layer having an aperture in a region corresponding to an electric connection region of the pad; and selectively etching the first and second insulating layers by using the mask layer as a mask to expose the electric connection region.
Still another embodiment relates to a method of fabricating a semiconductor device comprising: forming a pad with a predetermined pattern on an insulating layer; forming a protective insulating layer on the insulating layer over the pad; forming a mask layer on the protective insulating layer, the mask layer having an aperture in a region corresponding to an electric connection region of the pad; and patterning the protective insulating layer by isotropic etching with the mask layer as a mask to expose the electric connection region.
Another embodiment relates to a bonding pad structure including a bonding pad formed over a portion of a substrate and an insulating region formed over a portion of the bonding pad, wherein the bonding pad includes an area surrounded by and uncovered by the insulating region. The insulating region includes a side surface surrounding the uncovered area of the bonding pad, wherein at least part of the side surface is tapered and has an acute angle to a top surface of the bonding pad.
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patent: 5433823 (1995-07-01), Cain
patent: 5470793 (1995-11-01), Kalnitsky
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patent: 07-302797 (1995-11-01), None
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U.S. application Ser. No. 09/479,107 (filed Jan. 7, 2000).
Notice of Reasons of Rejection for Japanese Patent Application No. 2000-162322, dated Sep. 17, 2002 (from which priority is claimed for U.S. Ser. No. 09/607,219).
Konrad Raynes & Victor LLP
Quach T. N.
Raynes Alan S.
Seiko Epson Corporation
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