Measuring and testing – Surface and cutting edge testing – Roughness
Reexamination Certificate
2001-08-30
2004-08-24
Larkin, Daniel S. (Department: 2856)
Measuring and testing
Surface and cutting edge testing
Roughness
C073S104000, C356S600000, C382S108000, C382S147000, C382S149000, C382S150000, C382S154000
Reexamination Certificate
active
06779386
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims foreign priority benefits of Singapore Application No.
200104881-8
filed on Aug. 13, 2001.
BACKGROUND
The present invention relates to methods and apparatuses for detecting topographical features of microelectronic substrates, for example, detecting the surface roughness of a microelectronic substrate having solder or gold bump terminals. Packaged microelectronic assemblies, such as memory chips and microprocessor chips, typically include a microelectronic substrate die encased in a plastic, ceramic, or metal protective covering. The dies are typically formed in or on a wafer, such as a silicon wafer, and can include functional devices or features, such as memory cells, processing circuits, and interconnecting wiring. Each die also typically includes bond pads or other conductive structures, such as gold bumps or solder bumps that are electrically coupled to the functional devices. The conductive structures can then be electrically coupled to pins or other types of terminals that extend outside the protective covering for connecting to buses, circuits, and/or other microelectronic assemblies.
One method for increasing the throughput of packaged microelectronic assemblies is to perform many processing operations on the dies before the dies are singulated from the wafer, a practice referred to in the industry as wafer-level packaging. One such process step includes disposing gold or solder bumps on the dies at the wafer level to form a “bumped” wafer. When performing such operations at the wafer level, it is typically important to measure the average thickness, thickness variation, and roughness of the wafer to ensure that the wafer meets tight dimensional specifications, and to ensure that any microdefects of the wafer (which can reduce wafer strength) are eliminated or reduced to acceptable levels.
FIG. 1A
is a schematic illustration of a conventional apparatus
10
a
for measuring the thickness and thickness variation of a wafer
30
. Such apparatuses are available from ADE of Westwood, Mass., under model numbers 9520 and 9530. The apparatus
10
a
can include a narrow, rod-shaped vacuum chuck
12
that supports the wafer
30
, a lower capacitance probe
11
a
that measures the distance to the wafer back surface, and an upper capacitance probe
11
b
that measures the distance to the wafer front or device-side surface. The thickness of the wafer
30
at a particular point on the wafer can be calculated by subtracting the two distance measurements from the total distance between the capacitance probes
11
a
and
11
b
. The total thickness variation (TTV) of the wafer
30
can be calculated by traversing the rotating wafer
30
in between the probes
11
a
and
11
b
, determining a maximum thickness value and a minimum thickness value, and subtracting the minimum thickness value from the maximum thickness value. The average thickness of the wafer can be calculated by taking the mean of all the thickness values collected.
FIG. 1B
is a schematic illustration of an apparatus
10
b
used to determine the roughness of the wafer
30
. The apparatus
10
b
can include a support table
20
that carries the wafer
30
with the back surface of the wafer
30
facing upwardly. A stylus
41
traverses over the back surface of the wafer
30
and moves up and down as it passes over roughness features on the back surface. A light
12
illuminates the back surface of the wafer
30
for visual inspection through a microscope
13
which can be used to capture a video image that can be saved on a bitmap file for correlating with the capacitance scan data. Such apparatuses are available from Veeco-Metrology Group of Santa Barbara, Calif.
One drawback with the devices
10
a
and
10
b
described above is that they may not be suitable for detecting the characteristics of bumped wafers which have solder bumps or gold bumps that project from a surface of the wafer. For example, the apparatus
10
a
shown in
FIG. 1A
typically cannot distinguish between the surface of the wafer
30
and the elevated surface of the bumps on the wafer
30
, and can accordingly produce erroneous thickness and thickness variation measurements. The capacitance probes
11
a
and
11
b
typically do not have the high resolution required to determine surface roughness. The apparatus
10
b
shown in
FIG. 1B
typically includes a vacuum system in the support table
20
to draw the wafer
30
tightly down against the table
20
. When the wafer
30
includes solder bumps or gold bumps, the bumped surface of the wafer
30
may not form an adequate seal with the support table
20
. Furthermore, the contact between the support table
20
and the wafer
30
can damage the bumps and render all or part of the wafer
30
inoperable.
FIG. 1C
illustrates a conventional apparatus
10
c
available from August Technology of Bloomington, Minn., and specifically configured to detect characteristics of a bumped wafer
30
. The apparatus
10
c
can include a support table
20
having a vacuum system to draw the back surface of the wafer
30
down tightly against the support table
20
, with the bumps
34
facing upwardly. A two-dimensional inspection camera
43
traverses above the device-side surface of the wafer
30
to assess the position, diameter, and/or surface characteristics of the bumps
34
. A three-dimensional inspection camera
44
can traverse above the device-side surface of the wafer
30
to determine the height of the bumps
34
.
One drawback with the device
10
c
shown in
FIG. 1C
is that it is not configured to determine the thickness, the total thickness variation, or the roughness of the backside of the wafer
30
. Accordingly, none of the apparatuses described above with reference to
FIGS. 1A-C
are capable of adequately determining the characteristics of the wafer
30
typically used to assess whether the wafer
30
is ready for singulation and subsequent packaging operations.
SUMMARY
The present invention is directed toward apparatuses and methods for detecting characteristics of a microelectronic substrate having a first surface with first topographical features and a second surface facing opposite from the first surface and having second topographical features. In one aspect of the invention, the apparatus can include a support member configured to carry the microelectronic substrate with a first portion of the first surface exposed and a second portion of the second surface exposed. The apparatus can further include a topographical feature detector positioned proximate to the support member and aligned with a first portion of the first surface of the microelectronic substrate when the microelectronic substrate is carried by the support member. The topographical feature detector can include a non-capacitive detection device configured to detect roughness characteristics of the first topographical features.
In a further aspect of the invention, the apparatus can also include a second topographical feature detector positioned proximate to the support member and configured to detect a characteristic of the second topographical features. The second topographical features can include solder bumps or gold bumps, and the first topographical features can include a roughness element that is not a conductive connection structure. The second topographical feature detector can include a probe having a contact portion configured to contact the microelectronic substrate, or a radiation emitter and receiver configured to direct radiation toward the microelectronic substrate and receive reflected radiation to detect a roughness of the microelectronic substrate. The radiation emitter can be configured to emit laser radiation, and the radiation receiver can be configured to receive laser radiation.
The invention is also directed toward a method for detecting characteristics of a microelectronic substrate having a first surface with first topographical features that do not include conductive connection structures, and a second surface facing opposite from the first su
Ho Kian Seng
Neo Chee Peng
Tan Cher Khng Victor
Tan Hock Chuan
Larkin Daniel S.
Micro)n Technology, Inc.
Perkins Coie LLP
LandOfFree
Method and apparatus for detecting topographical features of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for detecting topographical features of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for detecting topographical features of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3353097