Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-18
2004-02-17
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S269000, C257S339000, C257S351000, C257S371000, C257S376000, C257S402000
Reexamination Certificate
active
06693331
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor manufacturing, and more particularly, the invention relates to complementary metal oxide semiconductor (CMOS) integrated circuits having at least two different threshold voltage n-channel field effect transistors (NFETs) and at least two different threshold p-channel field effect transistors (PFETs).
2. Background
Advances in semiconductor manufacturing technology have led to the integration of millions of circuit elements, such as transistors, on a single integrated circuit (IC). In order to integrate increasing numbers of circuit elements onto an integrated circuit it has been necessary to reduce the line widths of the various parts that make up an integrated circuit. Not only have interconnect line widths become smaller, but so have the dimensions of metal-oxide-semiconductor field effect transistors (MOSFETs).
MOSFETs are also sometimes referred to as insulated gate field effect transistors (IGFETs). Most commonly, these devices are referred to simply as FETs, and are so referred to herein.
Transistor scaling typically involves more than the linear reduction of the FET width and length. For example, both source/drain (S/D) junction depth and gate dielectric thickness are also typically reduced in order to produce a FET with the desired electrical characteristics. Additionally, as transistor dimensions scale down, the voltages at which they must operate are also be scaled down. Without scaling down supply voltages, the electric field imposed across the scaled down gate dielectric is increased, often leading to a rupture of the gate dielectric, and consequently leads to functional failure or reduced reliability of an integrated circuit. By scaling down the power supply voltages, the electric field across the gate dielectric is reduced thereby preventing damage due to electric field intensity. However, reduced supply voltages also reduces the gate drive and thereby reduces the obtainable circuit performance. To compensate for reduced gate drive in these scaled down integrated circuits it is common to also scale down the MOSFET threshold voltages.
Unfortunately, as the power supply voltage is scaled below, for example, 1.5 volts, the MOS transistor threshold voltage cannot be scaled to the same degree because of the undesirable off-state leakage current that occurs in low Vt (threshold voltage) transistors. Although the off-state current in a single transistor is not typically very large, integrated circuits such as microprocessors may have hundreds of millions of transistors and therefore it becomes extremely difficult to obtain low standby power consumption.
What is needed are transistors suitable for use in integrated circuits that provide high speed performance and low off state leakage currents.
SUMMARY OF THE INVENTION
Briefly, a method of forming an MOS integrated circuit having at least two types of NFET, each type having a different threshold voltage, and at least two types of PFET, each type having a different threshold voltage, includes forming at least four active regions in a substrate, each region having a different doping profile.
REFERENCES:
patent: 4532696 (1985-08-01), Iwai
patent: 5164805 (1992-11-01), Lee
patent: 5239197 (1993-08-01), Yamamoto
patent: 5254487 (1993-10-01), Tamagawa
patent: 5547894 (1996-08-01), Mandelman et al.
patent: 5548143 (1996-08-01), Lee
patent: 5557231 (1996-09-01), Yamaguchi et al.
patent: 5714796 (1998-02-01), Chishiki
patent: 5789788 (1998-08-01), Ema et al.
patent: 5795803 (1998-08-01), Takamura et al.
patent: 5827763 (1998-10-01), Gardner et al.
patent: 5847432 (1998-12-01), Nozaki
patent: 5952696 (1999-09-01), Gardner et al.
patent: 5963799 (1999-10-01), Wu
patent: 6090652 (2000-07-01), Kim
patent: 6111427 (2000-08-01), Fujii et al.
patent: 6187643 (2001-02-01), Borland
patent: 6207510 (2001-03-01), Abeln et al.
patent: 6287912 (2001-09-01), Asukura et al.
patent: 6337248 (2002-01-01), Imai
patent: 6342719 (2002-01-01), Arai
patent: 6455402 (2002-09-01), Lee et al.
patent: 6462385 (2002-10-01), Kumagai
patent: 0614222 (1994-02-01), None
patent: 10050860 (1998-02-01), None
patent: 849801 (1998-06-01), None
patent: 11004004 (1999-01-01), None
patent: 2 314974 (1998-01-01), None
patent: 2 314 974 (1998-01-01), None
patent: 2314974 (1998-01-01), None
patent: 8-204025 (1996-08-01), None
patent: 9-45792 (1997-02-01), None
patent: 10 50860 (1998-02-01), None
patent: 10 242292 (1998-09-01), None
patent: 11-4004 (1999-01-01), None
Mistry Kaizad R.
Post Ian R.
Flynn Nathan J.
Intel Corporation
Sefer Ahmed N.
Wheeler Cyndi M.
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