Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-02-28
2004-02-24
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C700S109000, C700S121000
Reexamination Certificate
active
06698009
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and, more particularly, to a method and apparatus using metrology data from an integrated source for modeling system dynamics within a process batch of semiconductor wafers.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today's manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging, and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed on a group of semiconductor wafers, sometimes referred to as a lot. For example, a process layer composed of a variety of materials may be formed above a wafer. Thereafter, a patterned layer of photoresist may be formed above the process layer using known photolithography techniques. Typically, an etch process is then performed on the process layer using the patterned layer of photoresist as a mask. This etching process results in formation of various features or objects in the process layer. Such features may be used for a gate electrode structure for transistors. Many times, trench structures are also formed on the substrate of the semiconductor wafer to isolate electrical areas on a semiconductor wafer. One example of an isolation structure that can be used is a shallow trench isolation (STI) structure. Typically, STI structures are formed on the semiconductor wafers by forming trenches in the wafer and filling such trenches with an insulating material, such as silicon dioxide.
The manufacturing tools within a semiconductor manufacturing facility typically communicate with a manufacturing framework or a network of processing modules. Each, manufacturing toot is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which a manufacturing network is connected, thereby facilitating communications between the manufacturing tool and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process.
FIG. 1
illustrates a typical semiconductor wafer
105
. The wafer
105
typically includes a plurality of individual semiconductor die
155
arranged in a grid
150
. Photolithography steps are typically performed by a stepper on approximately one to four die locations at a time, depending on the specific photomask employed. Photolithography steps are generally performed to form a patterned layer of photoresist above one or more process layers that are to be patterned. The patterned photoresist layer can be used as a mask during etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features or opening-type features that are to be replicated in an underlying process layer.
Turning now to
FIG. 2
, one example of a general block diagram representation of a typical manufacturing process flow is illustrated. A manufacturing lot or batch of semiconductor wafers
105
are processed (block
210
). After a lot/batch of wafers
105
are processed, generally, metrology data may then be acquired (block
220
). The metrology data is analyzed by a processing system. Based upon the analysis, the processing system determines whether there are any errors in the processed semiconductor wafers
105
(block
230
). Generally, the errors are determined based upon the aggregate data relating to the metrology data from the batch/lot of wafers
105
. In other words, the metrology data as a whole, is used to determine whether substantial errors exist on the processed semiconductor wafers
105
. Subsequently, the tool operation may be modified based upon the errors detected from the analysis of the metrology data (block
240
).
The errors that may be the basis for adjusting the operation of the tool may vary within a particular lot. Variations in the processing tool and/or the metrology tool may produce different errors within a batch of semiconductor wafers
105
. Often, a processing tool may process an initial set of wafers
105
in a batch slightly differently from subsequent wafers
105
in the batch, resulting in an initial wafer
105
effect. Furthermore, slight drifts in the processing and/or the metrology tool operation may cause a variation in the metrology data acquired within a batch of wafers
105
. Therefore, wholesale changes to the tool operation based upon the metrology data of an entire batch of semiconductor wafers
105
may not accurately adjust for errors that occur as a batch of wafers
105
progress through a processing step.
The present invention is directed to overcoming, or at least reducing, the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method is provided for performing modeling of batch dynamics in processing of semiconductor wafers. The method includes performing the process on the first semiconductor wafer in a lot, the process being controlled by a tool model, and acquiring integrated metrology data related to the process of the first semiconductor wafer using an integrated metrology tool. The method further includes performing a lot dynamic modeling process based upon an analysis of the integrated metrology data, the lot dynamic modeling process comprising adjusting the tool model based upon analysis of the integrated metrology data, and performing the process on a second semiconductor wafer in the lot based upon the adjusted tool model.
In another aspect of the present invention, a system is for performing modeling of batch dynamics in processing of semiconductor wafers. The system of the present invention comprises: a process controller adapted to adjust a process performed on a lot of semiconductor wafers based upon analysis of integrated metrology data analyzed by the process controller; an integrated metrology data storage unit operatively coupled to the process controller, the integrated metrology data storage unit adapted to receive and store integrated metrology data; a tool model operatively coupled to the process controller, the tool model adapted to control a processing operation on a lot of semiconductor wafers; and a process controller operatively coupled to the integrated metrology data storage unit and the tool model, the process controller adapted to adjust the tool model based upon analysis of the integrated metrology data received from the integrated metrology data storage unit.
In yet another aspect of the present invention, a computer readable program storage device encoded with instructions is for performing modeling of batch dynamics in processing of semiconductor wafers. The computer readable program storage device encoded with instructions when executed by a computer: performs a process on a first semiconductor wafer in a lot, the process being controlled by a tool model; acquires integrated metrology data related to the p
Bode Christopher A.
Pasadyn Alexander J.
Advanced Micro Devices , Inc.
Siek Vuthe
Williams Morgan & Amerson P.C.
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