Electrical computers and digital data processing systems: input/ – Intrasystem connection
Reexamination Certificate
1999-12-31
2004-02-24
Thai, Xuan M. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Reexamination Certificate
active
06697896
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of computer systems. More specifically, the present invention relates to high-speed signaling processing.
2. Description of the Related Art
With rapidly development of processor technologies, a faster bus implementation is needed to transfer data or control signals between processor components. Typically, a system contains multiple buses including processor and system buses and generally the buses are slower components in the system. Thus, in order to optimize a high-speed performance processor, high-speed buses are typically required.
A first approach to improve bus performance is to employ conventional scheme of differential signaling bus. A problem with this approach is that the differential signaling bus requires two additional reference signals for each data signal. Thus, this approach increases bus wires by at least two times, and consequently consumes a large amount of power and chip space to operate the additional wires.
A second approach to improve bus speed is to use conventional scheme of differential signaling bus where the reference signals are generated locally. A problem with this approach is that most of the signal margins needed to trigger the sense amplifier may be lost at the receiving end because the power supplies for the driver and the power supplies for the receiver are located far apart. Thus, the signal margins for this approach are required to increase and, accordingly, more power is required to operate this approach.
SUMMARY OF THE INVENTION
A device contains a first device and a second device. In one embodiment, the first device drives at least three signals, a first reference signal, and a second reference signal. The second device, which is coupled to the first device, receives the at least three signals, the first reference signal, and the second reference signal. The second device identifies values for the at least three signals according to the first reference signal and the second reference signal.
Additional features and benefits of the present invention will become apparent from the detailed description, figures and claims set forth below.
REFERENCES:
patent: 5220211 (1993-06-01), Christopher et al.
patent: 5818261 (1998-10-01), Perner
patent: 6154498 (2000-11-01), Dabral et al.
patent: 6282138 (2001-08-01), Wilkins
Intel Corporation
Thai Xuan M.
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