Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state
Reexamination Certificate
2002-09-17
2004-06-22
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to nonconductive state
C438S601000, C257S209000, C257S529000, C257SE23149
Reexamination Certificate
active
06753210
ABSTRACT:
BACKGROUND OF THE INVENTION
The thickness of the top aluminum (Al) layer on fuses tend to be thick, i.e. about 12,000 Å, because of the mechanical strength requirements for probing and bonding. If the fuse is formed with thick a top Al layer, the yield of the fuse operation, e.g. blowing open by a laser beam, tends to be low.
U.S. Pat. No. 6,261,873 B1 to Bouldin et al. describes a metal fuse with thick and thin segments.
U.S. Pat. No. 6,100,118 to Shih et al. describes a fuse guard ring method and structure.
U.S. Pat. No. 6,100,116 to Lee et al. describes a method to form a protected metal fuse by forming protection layers completely around the fuse.
U.S. Pat. No. 4,792,835 to Sacarisen et al. describes a process for making a metal fuse link in a MOS or CMOS process.
U.S. Pat. No. 6,037,648 to Arndt et al. describes a semiconductor structure including a conductive fuse and a process of fabricating the same.
U.S. Pat. No. 5,936,296 to Park et al. describes integrated circuits having metallic fuse links.
SUMMARY OF THE INVENTION
Accordingly, it is an object of one or more embodiments of the present invention to provide improved methods of forming metal fuses.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a structure is provided having exposed adjacent metal structures. A patterned dielectric layer is formed over the structure. The patterned dielectric layer having via openings exposing at least a portion of the exposed adjacent metal structures. A metal fuse portion is formed between at least two of the adjacent metal structures without additional photolithography, etch or deposition processes. The metal fuse portion including a portion having a nominal mass and a sub-portion of the portion having a mass less than the nominal mass so that the metal fuse portion is more easily disconnected at the less massive sub-portion during programming of the metal fuse portion.
REFERENCES:
patent: 4792835 (1988-12-01), Sacarisen et al.
patent: 5936296 (1999-08-01), Park et al.
patent: 6037648 (2000-03-01), Arndt et al.
patent: 6100116 (2000-08-01), Lee et al.
patent: 6100118 (2000-08-01), Shih et al.
patent: 6261873 (2001-07-01), Bouldin et al.
Hou Shang Y.
Jeng Shin-Puu
Wu Chi-Hsi
Ackerman Stephen B.
Coleman W. David
Saile George O.
Stanton Stephen G.
Taiwan Semiconductor Manufacturing Company
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