Semiconductor device manufacturing method of forming an...

Details Semiconductor device manufacturing method of forming an... Semiconductor device manufacturing method of forming an...

2002-01-28

2004-02-10

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S791000, C438S761000, C438S788000, C438S790000

Reexamination Certificate

active

06689690

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of Japanese Patent Applications No. 2001-203723, filed in Jul. 4, 2001, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device and, more particularly, to a semiconductor device having a multilayer interconnection structure, and a manufacturing method thereof.
As semiconductor integrated circuit devices have been becoming smaller in size, a multitude of semiconductor elements have come to be formed on a semiconductor substrate. A single interconnection layer is not sufficient to connect these numerous semiconductor elements. Accordingly, a multilayer interconnection structure laminated in a plurality of interconnection layers is used instead of such a single interconnection layer. A typical multilayer interconnection structure comprises a lamination of a multitude of interconnection layers each formed between insulating interlayer films. In this structure, the interconnection layers are connected by via holes formed in the insulating interlayer films.
Additionally, this multilayer interconnection structure has considerably complicated interconnection patterns corresponding to a multitude of semiconductor elements formed on a substrate. Accordingly, these interconnection patterns have a very large total length. As a result, the delay of an electric signal being transmitted through the interconnection patterns has become too large to ignore, and due to this signal delay, signal waveforms have been broken to a degree that cannot be disregarded. Thereupon, in order to minimize the signal delay in the multilayer interconnection structure, conventional technologies have attempted to use a low dielectric constant material as the insulating interlayer film. Also, in order to minimize an interconnect resistance, conventional technologies have attempted to use a low resistance material, especially Cu, as an interconnect material.
When Cu is used as the interconnect material, a damascene method has been employed, because an effective dry etching method has not been available yet. In the damascene method, grooves corresponding to interconnection patterns and via holes are formed beforehand in an insulating interlayer film; then, the grooves are filled with a Cu layer; and thereafter, part of the Cu layers existing on the surface of the insulating interlayer film is removed by a CMP (Chemical Mechanical Polishing) method.
2. Description of the Related Art
FIG. 1A
to
FIG. 3B
show a first conventional example of steps of forming a multilayer interconnection structure according to a dual damascene method.
In a step shown in
FIG. 1A
, an underlying interconnection pattern
10
, such as Cu, is formed on an Si substrate
1
with an insulating film (not shown in
FIG. 1A
to
FIG. 3B
) therebetween. A first etching stopper film
12
of SiN is formed on the underlying interconnection pattern
10
by a plasma CVD method. A first insulating interlayer film
14
of SiO
2
is formed on the SiN film
12
by the plasma CVD method. A second etching stopper film
16
of SiN is formed on the SiO
2
film
14
by the plasma CVD method. Further, a resist pattern
18
is formed on the SiN film
16
. A resist opening
18
A is formed in the resist pattern
18
at a position corresponding to a contact hole (
28
) to be formed in the multilayer interconnection structure.
Next, in a step shown in
FIG. 1B
, the SiN film
16
is subjected to a dry etching using the resist pattern
18
as a mask so as to form an opening
20
in the SiN film
16
. The opening
20
is formed at a position corresponding to the resist opening
18
A. After the opening
20
is formed, the resist pattern
18
is removed by ashing.
Next, in a step shown in
FIG. 1C
, an SiO
2
film
22
is so formed, as a second insulating interlayer film, on the SiN film
16
by a CVD method as to cover the opening
20
.
Subsequently, in a step shown in
FIG. 2A
, a resist pattern
24
having an opening
24
A is formed on the SiO
2
film
22
. The opening
24
A is at a position corresponding to an interconnection groove (
26
) to be formed in the SiO
2
film
22
so as to include the opening
20
formed in the SiN film
16
. In a step shown in
FIG. 2B
, the SiO
2
film
22
is subjected to a dry etching using the resist pattern
24
as a mask so as to form an interconnection groove
26
in the SiO
2
film
22
. At this point, the SiN film
16
and the opening
20
are exposed at the bottom of the interconnection groove
26
. The above-mentioned dry etching is continuously performed to the Sio
2
film
14
exposed in the opening
20
by using the SiN film
16
as a mask so as to form a contact hole
28
in the SiO
2
film
14
. The SiN film
12
is exposed at the bottom of the contact hole
28
.
Subsequently, in a step shown in
FIG. 2C
, the SiN film
12
exposed at the bottom of the contact hole
28
is removed by etching so that the Cu interconnection pattern
10
is exposed at the bottom of the contact hole
28
. In a step shown in
FIG. 3A
, the interconnection groove
26
and the contact hole
28
are filled by sputtering Cu and electroplated Cu. Further, in a step shown in
FIG. 3B
, a part of the Cu layer
29
above the surface of the second insulating interlayer film
22
is removed by a CMP method so as to leave a Cu pattern
29
A in the interconnection groove
26
and the contact hole
28
of the multilayer interconnection structure shown in FIG.
3
B.
In the above-described steps of forming the multilayer interconnection structure according to the dual damascene method, the interconnection groove
26
and the contact hole
28
are continuously formed by one dry etching process. This simplifies manufacturing steps of a semiconductor device.
FIG. 4A
to
FIG. 5C
show a second conventional example of steps of forming a multilayer interconnection structure. Elements in
FIG. 4A
to
FIG. 5C
that are described above are referenced by the same reference marks, and will not be described in detail.
In a step shown in
FIG. 4A
, an SiN film
30
is formed, as a first etching stopper film, on the Cu interconnection pattern
10
by a plasma CVD method. In this second example, an organic SOG film
32
is applied, as a first insulating interlayer film, on the SiN film
30
by such a method as a spin coating. An SiN film
34
is formed, as a second etching stopper film, on the organic SOG film
32
by the plasma CVD method. Further, an organic SOG film
36
is formed, as a second insulating interlayer film, on the SiN film
34
by the plasma CVD method.
Further, a resist pattern
38
having an opening
38
A is formed on the organic SOG film
36
. The opening
38
A is at a position corresponding to a contact hole (
40
) to be formed in the organic SOG film
32
.
Next, in a step shown in
FIG. 4B
, the organic SOG film
36
, the SiN film
34
and the organic SOG film
32
are etched by using the resist patter
38
as a mask so as to form a contact hole
40
.
Subsequently, in a step shown in
FIG. 4C
, a resist pattern
42
having an opening
42
A is formed on the organic SOG film
36
. The opening
42
A is at a position corresponding to an interconnection groove (
44
) to be formed in the organic SOG film
36
so as to include the contact hole
40
.
Subsequently, in a step shown in
FIG. 5A
, the organic SOG film
36
is etched by using the resist pattern
42
as a mask so as to form an interconnection groove
44
in the organic SOG film
36
. During this interconnection groove
44
being formed, the resist pattern
42
is removed by the organic SOG film
36
etching. As described above, the interconnection groove
44
includes the contact hole
40
. The interconnection groove
44
exposes the SiN film
34
at the bottom part thereof. The contact hole
40
exposes the SiN film
30
at the bottom thereof.
After the etching process in the step shown in
FIG. 5A
, a step shown in
FIG. 5B
is performed, in which the SiN film
34
exposed at the bottom p

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