Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2003-07-16
2004-11-16
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C365S185080
Reexamination Certificate
active
06819608
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory module which is made up of a volatile memory such as DRAM, SRAM or the like as well as a re-writable non-volatile memory such as E
2
PROM or the like.
2. Description of the Related Art
In recent information processing apparatuses such as personal computers, workstation server computers and the like, a main storage device has an increasingly larger storage capacity in line with a faster processing speed provided by a CPU and an increased number of bits processed thereby, resulting in employment of memory modules such as SIMM (Single Inline Memory Module), DIMM (Dual Inline Memory Module), MCP (Multi Chip Package) and the like.
FIG. 1
is a plan view illustrating an exemplary configuration of a memory module, and
FIG. 2
is a side view illustrating an exemplary configuration of another memory module.
As illustrated in
FIGS. 1 and 2
, each of the memory modules comprises a plurality of volatile memories
1
such as DRAM, and re-writable non-volatile memory
2
such as E
2
PROM, both of which are mounted on the same substrate
3
. Specifically,
FIG. 1
illustrates an exemplary configuration of SIMM (or DIMM), while
FIG. 2
illustrates an exemplary configuration of MCP which has non-volatile memory
2
stacked on volatile memory
1
.
These memory modules have a plurality of volatile memories
1
which are commonly applied with address signals A
0
-An (n is a positive integer) for writing/reading data; control signals RAS (Row address strobe command), CAS (Column address strobe command), WE (Write enable) for setting volatile memories
1
in a predetermined operation mode; and control signal CS (chip select) for selecting a memory to be activated. Each volatile memory
1
receives or delivers a DQ signal which is input/output data, and a DQM signal for masking the DQ signal in accordance with bits assigned to respective volatile memories
1
.
A bank refers to a parallelly accessible memory area in a memory module which is selected by control signal CS. For example, in DIMM, volatile memories
1
mounted on one side of a substrate are set to bank
0
, while non-volatile memories
1
mounted on the other side are set to bank
1
.
On the other hand, non-volatile memory
2
previously stores information such as the configuration, type, characteristics and the like of the associated memory module, which is used by a system (information processing apparatus or the like) that is equipped with the memory module.
Next, the configuration of volatile memories
1
illustrated in
FIGS. 1 and 2
will be described with reference to
FIGS. 3
to
7
. The volatile memory illustrated in
FIG. 3
shows an exemplary configuration of conventional SDRAM (Synchronous DRAM).
AS illustrated in
FIG. 3
, conventional volatile memory
1
comprises memory cell array (MC ARRAY)
11
composed of a plurality of memory cells MC for storing data; a plurality of sense amplifiers
12
each for reading data stored in associated memory cell MC; row decoder (X DEC)
13
and column decoder (Y DEC)
14
for decoding address signal ADD for accessing memory cell into which data is written or from which data is read; a plurality of column switches (Y SW)
15
each for turning on/off the output of associated sense amplifier
12
in accordance with the result of decoding by column decoder
14
; data latch circuit (D LAT)
16
for temporarily holding data which is to be written into memory cell MC; output latch circuit (O LAT)
17
for temporarily holding data read from memory cell MC; row address latch circuit (X ADD LAT)
18
for temporarily holding a row address supplied to row decoder
13
; column address latch circuit (Y ADD LAT)
19
for temporarily holding a column address supplied to column decoder
14
; command decoder (CMD DEC)
20
for decoding a control command supplied from the outside for setting volatile memory
1
in any of various operation mode; initial setting register (INT REG)
21
for holding mode setting information such as a CAS latency, a burst length and a burst type; control circuit (CONT)
22
for controlling a data write operation to memory cell array
11
and a data read operation from memory cell array
11
in response to an output signal of command decoder
20
; data input buffer circuit
23
for receiving data supplied from the outside to pass the received data to data latch circuit
16
; and data output buffer circuit
24
for delivering data fed from output latch circuit
17
to the outside.
In addition to normal memory cell area (NMC)
111
which is a memory cell area for normal use, memory cell array
11
also comprises redundant row memory cell area (X RNC)
112
and redundant column memory cell area (Y RNC)
113
which are formed with redundant memory cells for replacement in the event of a fault in any memory cell within normal memory cell area
111
.
Row decoder
13
comprises normal row decoder (X NDEC)
131
and redundant row decoder (X RDEC)
132
associated with normal memory cell area
111
and redundant row memory cell area
112
, respectively. Column decoder
14
in turn comprises normal column decoder (Y NDEC)
141
and redundant column decoder (Y RDEC)
142
associated with normal memory cell area
111
and redundant column memory cell area
113
, respectively. Column switch
15
further comprises normal column switch (Y NSW)
151
and redundant column switch (Y RSW)
152
associated with normal memory cell area
111
and redundant column memory cell area
113
, respectively.
As illustrated in
FIG. 4
, initial setting register
21
comprises n address latch circuits
210
1
-
210
n
for holding address signals A
0
-An on a bit-by-bit basis; and a plurality of mode latch circuits
211
for holding control signals /RAS, /CAS, /WE, /CS, respectively. In synchronization with clock CLK applied from the outside, initial setting register
21
delivers latch signals IA
0
-IAn, IA
0
B-IAnB, control signals /RAS, /CAS, /WE, /CAS and their inverted versions. It should be noted that though
FIG. 4
shows only one mode latch circuit
211
, mode latch circuits
211
are provided corresponding to control signals /RAS, /CAS, /WE, /CS, respectively.
Command decoder
20
comprises latency setting decoder
201
, burst length setting decoder
202
and burst type setting decoder
203
for decoding latch signals IA
0
-IAm, IA
0
B-IAmB (m is a positive integer smaller than n: m<n) out of latch signals IA
0
-IAn, IA
0
B-IAnB delivered from address latch circuits
210
1
-
210
n
for use as the mode setting information, to deliver mode setting results which include the CAS latency, burst length and burst type; mode register setting decoder
204
for decoding control signals /RAS, /CAS, /WE, /CS delivered from mode latch circuit
211
to deliver mode register activation signal MRS; delay circuit
205
for delaying clock signal CLK applied from the outside by a predetermined time; logical AND gate
206
for delivering logical AND of mode register activation signal MRS and the clock signal delivered from delay circuit
205
; and mode latch circuit
207
1
-
207
3
for holding output signals of latency setting decoder
201
, burst length setting decoder
202
and burst type setting decoder
203
in synchronization with a timing clock delivered from logical AND gate
206
.
Initial setting register
21
and command decoder
20
illustrated in
FIG. 4
function as mode registers, each of which holds data such as the CAS latency, burst length and burst type that are set using address signals A
0
-Am. Latency setting decoder
201
, burst length setting decoder
202
, and burst type setting decoder
203
deliver their respective decoding results when address signal Am+
1
is “0”. A latency signal, a burst length signal and a burst type signal delivered from mode latch circuits
207
1
-
207
3
, respectively, are held unchanged until next mode register activation signal MRS is delivered, or until the next mode setting is made.
As illustrated in
FIG. 5
, upon setting of the mode registers, control signals /RA
Elpida Memory Inc.
Hayes & Soloway P.C.
Hoang Huan
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