Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2002-11-14
2004-08-10
Le, Vu A. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S171000
Reexamination Certificate
active
06775173
ABSTRACT:
The present invention concerns matrix-addressable apparatus comprising one or more memory devices with multi-directionally switchable memory cells arranged in a passive matrix-addressable array, wherein the memory cells comprises a memory medium in the form of a ferroelectric or electret thin-film memory material capable of being polarized by an applied electric field and exhibiting hysteresis, wherein at least one memory device comprises at least two and not more than three electrode means, wherein the first electrode means of said at least one memory device being either the only memory device of the apparatus or the first of two or more memory devices therein, is provided on an insulating substrate.
From an architectural standpoint the passive matrix approach of memories with a polymer memory in sandwich between the electrode layers is more attractive than the 1T/1C approach of state of the art silicon memory architectures, partly because it represent denser lateral storage (4f2 vs. 6f2 and larger), but even more because it allows stacking of successive memory layers, e.g. controlled from joint substrate circuitry. However, it is still a fact that even the 4f2 design only renders a 25% areal fill factor. With 50 to 100% fill factor the need for more than one memory layer would be equally reduced, as will production complexity, yield and—cost. Also, using only one or two memory layers would reduce the effect of polymer postprocessing correspondingly and hence prevent the negative performance effects from such procedures.
The traditional approach to increase cell density is by reducing cell area. However, the smaller the cell footprint, the smaller the signal (and the lower the SNR), and the more sensitive and hence complex and real estate demanding the read-out circuitry (dominated by sense amps) will have to be. In fact it is considered extremely challenging to build crosspoint matrix systems of any kind with smaller line pitch than 0.30 &mgr;m-0.40 &mgr;m (cell size, 0.09 &mgr;m
2
).
A concern related to multi-layer stacking is planarization. Building successive layers on preceding ones gradually produces a “curvy/bumpy” topography which creates substantial problems in regard of lithography control and hence the ability to address and read out from cells (e.g. sense amps are designed relative to an expected cell area, if this, through non-uniform lithography, varies beyond certain limits, the signal cannot be read out reliably/the difference between ones and zeros more difficult to determine).
The architecture also defines how many mask steps are minimum required, the fewer the less costly the manufacturing. Reducing number of mask steps per bit is very important, the present polymer matrix requires 19 more mask steps than competing flash memories for a typical device having 8 memory layers, which means almost twice the costs to process such a wafer compared to state of the art CMOS processes for e.g. flash memories.
In a polymer crosspoint matrix memory using a vertical switching field, the morphology of the spinned polymer films largely decides the usability in memory applications. It is particularly challenging to maintain an optimal morphology in regard of ferroelectric properties when film thickness shrinks below 100 nm. At such thicknesses the films are much more sensitive to type of solvents used, spin and baking conditions, type and effect of interfacial/barrier layers, etc. Increasingly thinner films are desirable in order to reduce switching voltage, e.g. films need to be thinner than 30 nm in order to achieve switching voltages lower than 5V. Lower voltage levels are required in order to use progressively denser lithography and be compatible with related design rules, which also allows reduced power consumption. Low voltage is furthermore very attractive in polymer memories, since it allows more, eventually all, circuitry to be built underneath the passive memory matrix, which again reduces effective cell footprint by reducing overhead footprint, possibly to zero, making vias, connections, etc. easier to design and implement.
However, to make such thin films with acceptable uniformity/morphology and no shorts, is very demanding over large areas (like a wafer), also because important ferroelectric properties, like crystallinity, tend to detonate with thinner films, while leakage and sneak currents represent an increasing problem. This again seriously affects the memory properties, e.g. the level of switchable and remnant polarization (important for distinguishing between ones and zeros), switching endurance and switching speed. Especially high temperature performance (e.g. >60° C.) seems to be tremendously reduced.
But even thicker memory films experience a range of problems, similar, if not so expressed, to those of thinner films. The preferred and established film application approach is spin-coating, using an appropriate solvent. The choice of solvent, spin conditions, possible solvent residues, baking conditions relative to solvent choice, etc., represent a great challenge regarding obtaining the correct combination of parameters, a challenge which is even much greater when thin films are concerned. Solvents are necessary to use in order to obtain thin, uniform films on wafer substrates.
Due to the switching voltage dependence of film thickness (see below), with reduced film uniformity, the coercive field will vary accordingly, which will create problems during operation if the variations are larger than the designed maximum swing in voltage. On the other hand, the larger the swing (designed), the more complex the circuitry will need to be to handle it, with added costs in regard of real estate efficiency/production complexity/device cost.
Probably an even greater morphology concern is the fact that the polymer is exposed to substantial postprocessing, e.g. deposition of top electrodes, interfacial layers, vias connections, etc. in multi-layered memory stacks, and this represents a potentially severe negative impact on the polymer, which are very difficult to control properly, especially in a commercial manufacturing process.
The use of polymer and especially the fact that the electrodes rest directly onto this material which has a melting temp of approximately 150° C., result in problems when packaging is concerned. In a typical soldering process, temperature can reach as high as 210° C. (for limited periods), which cause problems for the architecture, since the polymer electrodes start to melt and float such that the electrode/polymer film interface may be seriously damaged.
The object of the present invention is thus to obviate the above-mentioned disadvantages and problems with prior art matrix-addressable memory devices with particularly polymer memory materials and as used in a matrix-addressable data storage device.
The object of the invention as well as further features and advantages are realized with a matrix-addressable apparatus according to the present invention which is characterized in that the first electrode means comprises parallel strip-like electrodes of width w and height h spaced apart and mutually electrically insulated by a portion of insulating thin-film material provided between the electrodes and covering the side edges thereof in a layer of thickness &dgr;, said thickness &dgr; being small fraction of the electrode width w, that the electrodes have a high aspect ratio h/w, that the first electrode means comprises a plurality of parallel recesses in the top surface thereof and oriented perpendicularly to the longitudinal axis of the electrodes with a width about equal to the electrode width w and extending downwards from the top surface of the electrodes to a distance h about one half of the height H of the latter, said recesses being mutually spaced apart by a distance approximately equal to the width w of the electrodes, that at least the side walls of said recesses are covered by a thin film of the memory material and the bottom surface thereof with the insulating thin film which optionally also can be formed by the memory mat
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